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Thanks @chrmarlyn for the test case. I was able to successfully load this design into Vivado 2025.1 and route the design. However, RWRoute in RapidWright has a number of issues that we need to resolve before it can route this design on its own. Although it is not working yet (give us some time), I don't believe there is a need to run anything but For now, I would recommend you simply route this design in Vivado while we work on getting this working in RapidWright. |
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Hello again RapidWright devs!
I have run into an issue when trying to perform inter-site routing on a DCP containing Xilinx’s Processor System Reset block (proc_sys_reset). The DCP was generated from the Vivado example project Versal CPM QDMA EP Design (Part based) from the built-in project catalogue, and the board that’s used is the xcvp1202-vsva2783-3HP-e-S. I am working with Vivado
2025.1.I have tried the following combinations of intra- and inter-site routing (on both the
masterand2025.1.2branch) and gotten three different error messages:1. Routing each site individually using
SiteInsts androuteSite()+ routing the whole design withRWRoute.routeDesignFullNonTimingDriven(), resulting in the following error:2. Routing each site individually using
SiteInsts androuteSite()+ doing partial routing withPartialRouter.routeDesignPartialNonTimingDriven(design, unrouted), also results in an error:3. Attempting to intra-site-route with
design.routeSites(), which throws the following error:If you have a moment to look into this, I’d really appreciate your help as it seems there might be a bug.
Here is my code and the relevant files:
vp120_test_placed.zip
Thanks in advance!
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