How should I get unrouted nets on the module instance level?

[Han-sok]

Hi, I am trying to learn how to route selected pins that are unrouted in the design using RapidWright.
To make a mock example, I synthesized the DMA PCIe example design and intentionally ripped the ports of "xdma_app_i" instance.
I stored the .dcp and .edn (EDIF export file) from Vivado and read those files in RapidWright.

However, when I open the design and search through the netlist, the nets that were ripped in Vivado are not there.
I can verify this by opening up the "net_list.txt" file I created.

Below is the Java code I am using to do that:

import com.xilinx.rapidwright.design.*;
import com.xilinx.rapidwright.design.SitePinInst;
import com.xilinx.rapidwright.edif.EDIFCell;
import com.xilinx.rapidwright.edif.EDIFCellInst;
import com.xilinx.rapidwright.edif.EDIFNet;
import com.xilinx.rapidwright.edif.EDIFPortInst;

import java.io.FileWriter;
import java.io.IOException;
import java.util.Collection;

public class RoutingTest {
    public static void main(String[] args) {
        String dcpPath = "/home/hansok/Projects/RW_practice/project_2/";
        Design design = Design.readCheckpoint(dcpPath + "today_test.dcp", dcpPath + "today_test.edn");

        System.out.println("Design loaded: " + design.getName());

        EDIFCell top_cell = design.getNetlist().getTopCell();
        EDIFCellInst cell_app = top_cell.getCellInst("xdma_app_i");

        // Store text to a file.
        String outputPath = "/home/hansok/Projects/RW_practice/project_2/net_list.txt";
        String filePath = dcpPath + "nets.txt";

        try (FileWriter writer = new FileWriter(outputPath)) {
            for (Net net : design.getNets()) {
                if (net.getName().startsWith("xdma_app_i")) {
                    continue;
                } else if (net.getName().startsWith("xdma_1_ex_i")) {
                    continue;
                } else {
                    writer.write(net.getName() + "\n");
                }
            }
            System.out.println("Net list written to: " + outputPath);
        } catch (IOException e) {
            System.err.println("Failed to write net list: " + e.getMessage());
        }

        for (Net n : design.getNets()) {
            if (n.getName().startsWith("m_axi")) {
                for (SitePinInst pin : n.getPins()) {
                    if (!pin.isRouted() && !pin.isOutPin()) {
                        System.out.println("Net " + n.getName() + " has unrouted pin: " + pin.getName() + " in tile: " + pin.getTile().getName());
                    }
                }
            }
        }

    }
}

If I reopen the design in Vivado, those nets are still there, and I can highlight them with the Tcl command,
highlight_objects -color red [get_nets * -filter {ROUTE_STATUS == UNROUTED}].
and I can see the highlighted nets as shown in the screenshot below.

Should I create a fake routing to some register for those ripped nets and store the .dcp file again to make those unrouted nets visible in RapidWright?
Please let me know the correct way to achieve this.

Thank you.

Best,
Han-sok

[clavin-xlnx]

Hi Han-sok,

There are two net representations in RapidWright, physical nets and logical nets. Physical nets are represented by the Net object class and appears to be the objects that you are querying in RapidWright. When you describe "ripped" nets in Vivado, do you mean that you unrouted the nets? If that is the case, they may not show up in the list if they are not routed.

The second net representation are logical nets. These are represented by EDIFNet and EDIFHierNet and are directly related to the hierarchical netlist nets that are described in the EDIF or viewable in the Schematic Viewer in Vivado (see https://www.rapidwright.io/docs/RapidWright_Overview.html#net for more details). As many logical nets can map to a single physical net, we typically will name the physical net after the parent net of all the logical aliases. The parent net is the net that is most closely connected to the source pin of the net. If you wanted to print out all the logical parent nets of a design you could use this example code:

Set<EDIFHierNet> allParentNets = new HashSet<>(design.getNetlist().getParentNetMap().values());
for (EDIFHierNet parentNet: allParentNets) { 
    System.out.println(parentNet.toString());
}

You could also use the NetlistBrowser to view a graphical tree view of the netlist and try to find the nets there. You can run it at the command line with rapidwright NetlistBrowser <your dcp file> (this assumes that you have RapidWright installed and on your PATH).

Another problem you may encounter is that RapidWright cannot look inside encrypted cells. Typically, all IP blocks will be encrypted, so if the nets you are trying to find are inside the IP block, you probably won't be able to see them inside RapidWright.

Reach out with more questions. Hope that helps.

Chris

[Han-sok]

Hi Chris,

I appreciate your quick reply.

Yes, I intentionally disconnected selected nets in Vivado and saved that design in .dcp format to use with RapidWright. Regarding nets inside IPs, I am not trying to route those internal connections. My focus is on the ports of module instances (in Verilog) and connecting those ports to other module instances. For now, I’m learning and testing how to route specific ports of my choice to the ports of other modules. Eventually, my goal is to insert a pre-synthesized interconnect module to help RapidWright connect those ports more efficiently.

I’ll experiment with your suggestion and follow up once I’ve applied it to my setup. At the moment, I’m dealing with a configuration issue in IntelliJ that prevents me from running NetlistBrowser, which is only available in the latest RapidWright branch. (My original post was based on an older version of RapidWright because of this error.)

I’ll get back to you with a follow-up question after I make progress. Thank you again for your help.

Han-sok