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Invokes DREAMPlaceFPGA to place an EDIFNetlist and return a Design object. Requires that the dreamplacefpga binary be available on PATH.

Design is exported to DREAMPlaceFPGA using the FPGA Interchange Format, and imported back into RapidWright using this same format.

clavin-xlnx and others added 18 commits January 8, 2025 17:03
Signed-off-by: Chris Lavin <[email protected]>
* disable routability_opt

Signed-off-by: Zhili Xiong <[email protected]>

* fix result path and out_of_context flag

Signed-off-by: Zhili Xiong <[email protected]>

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Signed-off-by: Zhili Xiong <[email protected]>
Co-authored-by: Zhili Xiong <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
instead of DCP. Also call Design.routeSites() on result

Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
public static final String ENABLE_IF = "enable_if";
public static final String ENABLE_SITE_ROUTING = "enable_site_routing";

public static final String IO_PL_DEFAULT = "";
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Suggested change
public static final String IO_PL_DEFAULT = "";
public static final String IO_PL_DEFAULT = ""; //EMPTY

I'm assuming we meant to have an empty string here.

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4 participants