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Add double pumped compute and memory #1169

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Add double pumped compute and memory #1169

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4c7288d
[Transform] Skip broadcasting of thresholds in onnx conversion and ex…
auphelia Jun 10, 2024
85f98fd
Merge branch 'dev' into custom/bert
auphelia Jun 11, 2024
1906498
Merge branch 'dev' into custom/bert
auphelia Jun 12, 2024
7f296bd
Merge branch 'feature/per_tensor_rtl_thresh' into custom/bert
auphelia Jun 14, 2024
933b4eb
[MVAU] Initial draft of pumped compute for RTL MVU
auphelia Jun 13, 2024
89e5c82
[Transform] Add commands to ip stitching for second clk
auphelia Jun 18, 2024
c54a8b4
[Deps] Change pyverilator commit to enable second clock simulation
auphelia Jun 18, 2024
0ec5e58
[Util] Add v80 to versal list
auphelia Jun 20, 2024
1a24b36
[MVAU] Comment out assert for uram mem mode
auphelia Jun 24, 2024
0f7706f
[RTL MVAU] Allow for 4bit compute with dsp48 for versal devices
auphelia Jul 8, 2024
550499e
Merge branch 'dev' into feature/double_pumping_mem
auphelia Jul 8, 2024
69de66c
[CustomOp] Enable double pumped memstream for MVAU
auphelia Jul 9, 2024
edb6991
Merge dev into feature/double_pumping_mem
auphelia Aug 22, 2024
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2 changes: 1 addition & 1 deletion fetch-repos.sh
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@
QONNX_COMMIT="2281a777d84aa5cbd7469085c2e534fb4a03ccf9"
FINN_EXP_COMMIT="0724be21111a21f0d81a072fccc1c446e053f851"
BREVITAS_COMMIT="84f42259ec869eb151af4cb8a8b23ad925f493db"
PYVERILATOR_COMMIT="ce0a08c20cb8c1d1e84181d6f392390f846adbd1"
PYVERILATOR_COMMIT="4a38eea96540ce4f48c6ed26615593ba4e5fc67f"
CNPY_COMMIT="4e8810b1a8637695171ed346ce68f6984e585ef4"
HLSLIB_COMMIT="16e5847a5e3ef76cffe84c8fad2f010d593457d3"
OMX_COMMIT="0b59762f9e4c4f7e5aa535ee9bc29f292434ca7a"
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161 changes: 109 additions & 52 deletions finn-rtllib/memstream/component.xml
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2 changes: 1 addition & 1 deletion finn-rtllib/memstream/gui/memstream_v1_0.gtcl
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Original file line number Diff line number Diff line change
@@ -1,2 +1,2 @@
# This file is automatically written. Do not modify.
proc gen_USERPARAMETER_AXILITE_ADDR_WIDTH_VALUE {DEPTH WIDTH } {expr 2 + ceil(log($DEPTH*pow(2, ceil(log(($WIDTH+31)/32)/log(2))))/log(2))}
proc gen_USERPARAMETER_AXILITE_ADDR_WIDTH_VALUE {DEPTH WIDTH } {expr ceil(log($DEPTH*(2**ceil( log(($WIDTH+31)/32)/log(2) )))/log(2)) + 2}
308 changes: 0 additions & 308 deletions finn-rtllib/memstream/hdl/Q_srl.v
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