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Increase rtl and fifo-depth sim timeouts (fixes #1457)#1458

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auphelia merged 1 commit intoXilinx:devfrom
LeahLS:feature/aupzu3-integration
Nov 27, 2025
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Increase rtl and fifo-depth sim timeouts (fixes #1457)#1458
auphelia merged 1 commit intoXilinx:devfrom
LeahLS:feature/aupzu3-integration

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@LeahLS
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@LeahLS LeahLS commented Oct 16, 2025

Slightly increased the rtl and fifo-depth simulation timeouts to fix issue #1457 to not run into simulation timeouts when building the upscaled bnn-pynq finn-examples for the AUP-ZU3 board.

@fpjentzsch
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FYI: We had similar problems but worked around them differently, by letting LIVENESS_THRESHOLD (defaults to 1M) override this heuristic if it is larger: eki-project#115

@auphelia
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Thanks for pointing this out @fpjentzsch. We’ll proceed with @LeahLS's version for now because we want to avoid overriding behavior that we actually want to observe. If we replace the estimation with 1M, we might miss cases where a component changes the cycle count significantly and our estimation becomes too inaccurate.

@auphelia auphelia merged commit 40eb158 into Xilinx:dev Nov 27, 2025
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@fpjentzsch
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@auphelia Okay, although I think we should ideally detect mismatches between actual and estimated latency/interval via some kind of is-close comparison in the PyTests or in separate regression tests, not via detecting a simulation timeout.

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3 participants