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Adds reset after execution prehook in rtlsim #1460

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Merged
Parent: Release merge for v0.10.1
merged 2 commits into from
Oct 21, 2025
Merged

Adds reset after execution prehook in rtlsim #1460

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5eaaee3
[finn-rtllib] Propagate SETS through memstream components
auphelia Oct 2, 2025
b197a3d
[rtlsim exec] Add reset after running prehook fct
auphelia Oct 21, 2025
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2 changes: 1 addition & 1 deletion finn-rtllib/memstream/hdl/memstream.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@
*/

module memstream #(
int unsigned SETS = 1,
int unsigned SETS,
int unsigned DEPTH,
int unsigned WIDTH,

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4 changes: 3 additions & 1 deletion finn-rtllib/memstream/hdl/memstream_axi.sv
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Expand Up @@ -31,7 +31,7 @@
*/

module memstream_axi #(
int unsigned SETS = 1,
int unsigned SETS,
int unsigned DEPTH,
int unsigned WIDTH,

Expand Down Expand Up @@ -153,6 +153,7 @@ module memstream_axi #(
assign m_axis_0_tdata = mem_dat;

memstream #(
.SETS(SETS),
.DEPTH(DEPTH_EFF),
.WIDTH(WIDTH_EFF),
.INIT_FILE(INIT_FILE),
Expand Down Expand Up @@ -274,6 +275,7 @@ module memstream_axi #(
end : blkStreamOut

memstream #(
.SETS(SETS),
.DEPTH(DEPTH_EFF),
.WIDTH(WIDTH_EFF),
.INIT_FILE(INIT_FILE),
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1 change: 1 addition & 0 deletions src/finn/core/rtlsim_exec.py
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Expand Up @@ -357,6 +357,7 @@ def rtlsim_exec_finnxsi(model, execution_context, pre_hook=None, post_hook=None)
finnxsi.reset_rtlsim(sim)
if pre_hook is not None:
pre_hook(sim)
finnxsi.reset_rtlsim(sim)
n_cycles = finnxsi.rtlsim_multi_io(
sim,
io_dict,
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2 changes: 1 addition & 1 deletion tests/fpgadataflow/test_fpgadataflow_elementwise_binary.py
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Expand Up @@ -232,7 +232,7 @@ def test_elementwise_binary_operation(
if op_type in ["ElementwiseAdd", "ElementwiseSub", "ElementwiseMul"]:
# Equivalence checking is more relaxed for arithmetic operations
# numpy casts fp16 to fp32, computes in fp32, casts result to fp16
assert np.allclose(o_expected, o_produced, rtol=1e-3, atol=2**-14)
assert np.allclose(o_expected, o_produced, rtol=1e-3, atol=2**-13)
else:
assert np.all(o_expected == o_produced)
else:
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5 changes: 0 additions & 5 deletions tests/fpgadataflow/test_fpgadataflow_mvau.py
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Expand Up @@ -511,11 +511,6 @@ def test_fpgadataflow_mvau_large_depth_decoupled_mode_rtlsim(
pytest.skip("Temporarily xfail this test, because last address can't be read back.")
if preferred_impl_style == "rtl" and act is not None:
pytest.skip("RTL-MVAU doesn't support const mem mode or embedded activations")
if preferred_impl_style == "hls" and ram_style == "ultra" and not is_versal(part):
# reference: https://github.com/Xilinx/finn/issues/1312
pytest.skip(
"Known error for runtime writeable weights and HLS MVU. Described in issue 1312"
)
if nf == -1:
nf = mh
if sf == -1:
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4 changes: 2 additions & 2 deletions tests/fpgadataflow/test_fpgadataflow_thresholding_runtime.py
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Expand Up @@ -192,7 +192,7 @@ def test_runtime_thresholds_read(impl_style, idt_act_cfg, cfg, narrow, per_tenso
in_tensor = gen_finn_dt_tensor(idt, tuple(n_inp_vecs + [ch]))
in_tensor = np.tile(in_tensor, (2, 1, 1, 1))

exec_ctx = {"inp": in_tensor}
exec_ctx = {model.graph.input[0].name: in_tensor}
extracted_weight_stream = []

def read_weights(sim):
Expand Down Expand Up @@ -311,7 +311,7 @@ def test_runtime_thresholds_write(impl_style, idt_act_cfg, cfg, narrow, per_tens
in_tensor = gen_finn_dt_tensor(idt, tuple(n_inp_vecs + [ch]))
in_tensor = np.tile(in_tensor, (2, 1, 1, 1))

exec_ctx_write = {"inp": in_tensor}
exec_ctx_write = {model.graph.input[0].name: in_tensor}

def write_weights(sim):
addr = 0
Expand Down