Lowering of llvm trunc instruction

[newling]

The following snippet of LLVM IR:

; I think this is: load 512 bits, interpret as 16xi32, truncate to 16xi16, store 256 bits.
define void @func_0(){
  %1 = load <8 x i64>, ptr @buff_src, align 256
  %2 = tail call <16 x i16> @llvm.aie2.I256.v16.acc32.srs(<8 x i64> %1, i32 0, i32 0)
  store <16 x i16> %2, ptr @buff_dst, align 256
  ret void
}

Makes use of the SRS (shift-round-saturate) instruction for AIE2. with what I think is

shift = 0 (first i32 operand)
round = not relevant, as we're not doing floating point math
saturate = do not saturate (do we need to set another register for this?)

The above compiles fine with

llc test.ll  -O2 --march=aie2 --filetype=asm  -o test.s

As far as I can see, the following generic LLVM IR in exactly equivalent. Would it possible to perform instruction selection to make it compile to the same thing?

define void @func_1() { 
  %1 = load <16 x i32>, ptr @buff_src, align 256
  %2 = trunc <16 x i32> %1 to <16 x i16>
  store <16 x i16> %2, ptr @buff_dst, align 256
  ret void
}

Currently code like the above fails to compile, errors with

virtual const llvm::RegisterBankInfo::InstructionMapping&
llvm::AIE2RegisterBankInfo::getInstrMapping(const llvm::MachineInstr&)
const: Assertion `(DstTy == S16 || DstTy == S20 || DstTy == S32) && 
(SrcTy == S32 || SrcTy == S64) && "Expected to see 
only 32-or-64 to 16-or-20-or-32 bit truncations"' failed.

Note: there is some (oldish) public documentation for SRS the instruction here https://www.xilinx.com/htmldocs/xilinx2023_2/aiengine_ml_intrinsics/intrinsics/group__intr__gpvectorconv__srs.html -- if you're reading this and have a more up-to-date version please let me know and I'll update this link.

[konstantinschwarz]

We implemented generic trunc support in AIE2p, but took a slightly different approach: we aren't using SRS, but use VSHUFFLE instead to select the low bits from each lane: https://github.com/Xilinx/llvm-aie/blob/aie-public/llvm/lib/Target/AIE/aie2p/AIE2PInstrPatterns.td#L1256

A similar approach can be implemented for AIE2, but we first need to lift the regbankselect restriction

[newling]

That's great, thanks @konstantinschwarz

[newling]

A similar approach can be implemented for AIE2, but we first need to lift the regbankselect restriction

Can you provide a bit information/reference about this restriction? Mostly because I'm curious. Supporting this on AIE2 isn't high priority (for us), but if I understand the problem well enough I might like to get it working

[newling]

I suppose generic zext could also be supported with VSHUFFLE (using the 'high' modes). We'd quite like support for generic sext. That might be doable with UPS, if I understand the sign extension correctly.