Trace not generated when building some designs with peano (CHESS=false)

[jackl-xilinx]

This is an issue with the non-chess compile flow (peano) which seems to cause issues generating trace on some designs. Most notably, the simplified vector_scalar_mul design under section-4b. This would be enabled for designs if CHESS=false is passed to the make trace command. This is still being investigated but one workaround is to modify the aiecc.py build script to remove some optimization flags for the peano build option.

If you install your design via the utils/quick_setup.sh script, the source python file will be found under mlir-aie/my_install/mlir_aie/python/aie/compiler/aiecc/main.py.

Modify line 1137 to change:

await self.do_call(progress_bar.task, [self.peano_opt_path, "--passes=default<O2>", "-inline-threshold=10", "-S", file_llvmir, "-o", file_llvmir_opt])

to

await self.do_call(progress_bar.task, [self.peano_opt_path, "-S", file_llvmir, "-o", file_llvmir_opt])

to remove the two options.

[jackl-xilinx]

This should now be fixed in #2058 which requires adding trace_utils.gen_trace_done_aie2(ShimTile) at the end of the of the runtime_sequence and requires use of packet routed tracking instead of circuit routed tracing.