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@YanceyA YanceyA commented Nov 1, 2025

Summary

  • treat the STM32F411 configuration the same as the STM32F401 for peripheral clock dividers
  • ensure the STM32F411 uses the STM32F40x PLL setup path with pllp = 4 to maintain the 96 MHz SYSCLK and 48 MHz USB clock

Testing

  • not run (not requested)

https://chatgpt.com/codex/tasks/task_e_69057cb165688333b9a50db7bbc1d87f

@YanceyA YanceyA changed the title Treat STM32F411 like STM32F401 for clock setup Treat STM32F411 like STM32F401 for clock setup - #1 Nov 1, 2025
@YanceyA YanceyA changed the base branch from master to STM32F411_support November 1, 2025 03:42
@YanceyA YanceyA merged commit 747f332 into STM32F411_support Nov 1, 2025
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2 participants