Blackbox memory with simulation model.

[ben-j-c]

I want to have a large memory that isn't synthesized, but the CLI seems to imply that its doing considerable work inside. The invocation of hierarchy results in a warning which I do not expect.

My workaround is to use the commented out define, and then mark the used wires as (*keep*) .

Is there a way to instruct Yosys to not elaborate blackboxes?

read_verilog fabric.v

read_verilog -lib v2f_programmable_ram.v
hierarchy -libdir ./  -check -top fabric

This prints

ben@papaya:~/repo/verilog2factorio/examples/riscv_v2f_optimized/top_v2f$ yosys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <[email protected]>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.52 (git sha1 fee39a328, g++ 13.3.0-6ubuntu2~24.04 -fPIC -O3)

yosys> 

yosys> read_verilog fabric.v

1. Executing Verilog-2005 frontend: fabric.v
Parsing Verilog input from `fabric.v' to AST representation.
Generating RTLIL representation for module `\fabric'.
Successfully finished Verilog frontend.

yosys> read_verilog -lib /home/ben/repo/verilog2factorio/v2flib/v2f_programmable_ram.v

2. Executing Verilog-2005 frontend: /home/ben/repo/verilog2factorio/v2flib/v2f_programmable_ram.v
Parsing Verilog input from `/home/ben/repo/verilog2factorio/v2flib/v2f_programmable_ram.v' to AST representation.
Generating RTLIL representation for module `\v2f_programmable_ram'.
Warning: Replacing memory \memory with list of registers. See /home/ben/repo/verilog2factorio/v2flib/v2f_programmable_ram.v:0, /home/ben/repo/verilog2factorio/v2flib/v2f_programmable_ram.v:86
Successfully finished Verilog frontend.

yosys> hierarchy -libdir /home/ben/repo/verilog2factorio/v2flib  -libdir ../core/riscv  -check -top fabric

3. Executing HIERARCHY pass (managing design hierarchy).

3.1. Analyzing design hierarchy..
Top module:  \fabric

3.2. Analyzing design hierarchy..
Top module:  \fabric
Removed 0 unused modules.
Warning: Replacing memory \memory with list of registers. See /home/ben/repo/verilog2factorio/v2flib/v2f_programmable_ram.v:125, /home/ben/repo/verilog2factorio/v2flib/v2f_programmable_ram.v:0, /home/ben/repo/verilog2factorio/v2flib/v2f_programmable_ram.v:86
<60+ seconds>^C

Here are the files

v2f_programmable_ram.v

(* blackbox *)
module v2f_programmable_ram(
		RD_CLK,
		RD_EN,
		RD_ARST,
		RD_SRST,
		RD_ADDR,
		RD_DATA,
		WR_CLK,
		WR_EN,
		WR_ADDR,
		WR_DATA,
		BYTE_SELECT,
		ARST
	);
	parameter MEMID = "";
	parameter PROGRAM_FILE = "program.mem";
	parameter signed SIZE = 4;
	localparam signed OFFSET = 0;
	parameter signed ABITS = 2;
	localparam signed WIDTH = 32;
	localparam signed BYTE_WIDTH = 8;
	localparam signed INIT = 32'b0;

	parameter signed RD_PORTS = 1;
	parameter RD_CLK_ENABLE = 1'b1;
	parameter RD_CLK_POLARITY = 1'b1;
	localparam RD_TRANSPARENCY_MASK = 0;
	parameter RD_CE_OVER_SRST = 1'b0;

	localparam signed WR_PORTS = 1;
	localparam WR_CLK_ENABLE = 1'b1;
	localparam WR_CLK_POLARITY = 1'b1;

	input [RD_PORTS-1:0] RD_CLK;
	input [RD_PORTS-1:0] RD_EN;
	input [RD_PORTS-1:0] RD_ARST;
	input [RD_PORTS-1:0] RD_SRST;
	input [RD_PORTS*ABITS-1:0] RD_ADDR;
	output reg [RD_PORTS*WIDTH-1:0] RD_DATA;

	input [WR_PORTS-1:0] WR_CLK;
	input [WR_PORTS-1:0] WR_EN;
	input [WR_PORTS*ABITS-1:0] WR_ADDR;
	input [WR_PORTS*WIDTH-1:0] WR_DATA;
	input ARST;
	input [3:0] BYTE_SELECT;

//`ifndef YOSYS

	reg [WIDTH-1:0] memory [SIZE-1:0];

	integer i, j, k;
	reg [WR_PORTS-1:0] LAST_WR_CLK;
	reg [RD_PORTS-1:0] LAST_RD_CLK;

	function port_active;
		input clk_enable;
		input clk_polarity;
		input last_clk;
		input this_clk;
		begin
			casez ({clk_enable, clk_polarity, last_clk, this_clk})
				4'b0???: port_active = 1;
				4'b1101: port_active = 1;
				4'b1010: port_active = 1;
				default: port_active = 0;
			endcase

		end

	endfunction


	initial begin
		for (i = 0; i < SIZE; i = i+1)
			memory[i] = 0;
		RD_DATA = 0;
	end


	always @(*) begin
	`ifdef SIMLIB_MEMDELAY
		#`SIMLIB_MEMDELAY;
	`endif

		for (i = 0; i < RD_PORTS; i = i+1) begin
			if (RD_CLK_ENABLE[i] && RD_EN[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i])) begin
				// $display("Read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
				RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
			end
		end


		if (ARST) begin
			$readmemh(PROGRAM_FILE, memory, 0, SIZE-1);
		end
		else begin
			for (i = 0; i < WR_PORTS; i = i+1) begin
				if (port_active(WR_CLK_ENABLE[i], WR_CLK_POLARITY[i], LAST_WR_CLK[i], WR_CLK[i]))
					for (j = 0; j < WIDTH; j = j+1)
						if (WR_EN[i]) begin
							//$display("j=%d", j);
							if (BYTE_SELECT[j/BYTE_WIDTH]) begin
								memory[WR_ADDR][j] = WR_DATA[i*WIDTH+j];
								//$display("Write to %s: addr=%b data=%b, bs=%b, j=%d", MEMID, WR_ADDR[i*ABITS +: ABITS], WR_DATA[i*WIDTH+j], BYTE_SELECT, j);
							end
						end
			end
		end


		for (i = 0; i < RD_PORTS; i = i+1) begin
			if (!RD_CLK_ENABLE[i]) begin
				// $display("Combinatorial read from %s: addr=%b data=%b", MEMID, RD_ADDR[i*ABITS +: ABITS],  memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET]);
				RD_DATA[i*WIDTH +: WIDTH] <= memory[RD_ADDR[i*ABITS +: ABITS] - OFFSET];
			end
		end


		for (i = 0; i < RD_PORTS; i = i+1) begin
			if (RD_SRST[i] && port_active(RD_CLK_ENABLE[i], RD_CLK_POLARITY[i], LAST_RD_CLK[i], RD_CLK[i]) && (RD_EN[i] || !RD_CE_OVER_SRST[i]))
				RD_DATA[i*WIDTH +: WIDTH] <= 0;
			if (RD_ARST[i])
				RD_DATA[i*WIDTH +: WIDTH] <= 0;
		end
		LAST_RD_CLK <= RD_CLK;
		LAST_WR_CLK <= WR_CLK;
	end
//`endif
endmodule

fabric.v

module fabric
	(
	input clk,
	input arst,

	input instr_en,
	input instr_flush,
	input instr_invalidate,
	input [31:0] instr_addr,
	output [31:0] instr_q,
	output instr_accept,
	output reg instr_valid,
	output reg instr_error,

	input data_en,
	input [31:0] data_addr,
	input [31:0] wr_data,
	input [3:0] wr_bs,
	input [10:0] data_tag_d,
	output [31:0] data_q,
	output data_accept,
	output reg data_valid,
	output reg data_error,
	output reg data_ack,
	output reg [10:0] data_tag_q,

	input [15:0] inspect_addr,
	output [31:0] inspect_q,

	output [31:0] vram_addr,
	output [31:0] vram_data,
	output [3:0] vram_bs,
	output vram_en
);
	localparam ABITS = 16;
	localparam BEGIN_VRAM = 32'h00040000;
	localparam END_VRAM = 32'h00080000;

	assign instr_accept = 1'b1;
	(*keep*) wire instr_valid_internal = instr_addr < (4 << ABITS);
	always @(posedge clk, posedge arst) begin 
		if (arst) begin
			instr_valid <= 0;
			instr_error <= 0;
		end
		else if (instr_en) begin
			instr_valid <= instr_valid_internal;
			instr_error <= !instr_valid_internal;
		end
	end

	wire data_dst = data_addr < (4 << ABITS);
	wire vram_dst = data_addr >= BEGIN_VRAM && data_addr < END_VRAM;
	wire rd_wr_en = |wr_bs || data_en;
	assign data_accept = 1'b1;
	(*keep*)wire data_valid_internal = data_dst || vram_dst; // BUG: This seems to be needed as keep
	always @ (posedge clk, posedge arst) begin
		if (arst) begin
			data_valid <= 0;
			data_error <= 0;
			data_ack <= 0;
			data_tag_q <= 0;
		end
		else if (rd_wr_en) begin
			data_valid <= data_valid_internal;
			data_error <= !data_valid_internal;
			data_ack <= (|wr_bs || data_en) && data_valid_internal;
			data_tag_q <= data_tag_d;
		end
	end

	assign vram_addr = data_addr;
	assign vram_data = wr_data;
	assign vram_bs = wr_bs;
	assign vram_en = vram_dst;

	v2f_programmable_ram #(
			.SIZE(1 << ABITS),
			.PROGRAM_FILE("program.mem"),
			.ABITS(ABITS),
			.RD_PORTS(3),
			.RD_CLK_ENABLE(3'b110),
			.RD_CLK_POLARITY(3'b110)
		) ram (
		.RD_CLK({clk, clk, 1'b0}),
		.RD_EN({instr_en, data_en, 1'b0}),
		.RD_ARST({arst, arst, 1'b0}),
		.RD_SRST(3'b0),
		.RD_ADDR({instr_addr[17:2], data_addr[17:2], inspect_addr[15:0]}),
		.RD_DATA({instr_q, data_q, inspect_q}),
		.WR_CLK(clk),
		.WR_EN(|wr_bs && data_dst),
		.WR_ADDR(data_addr[17:2]),
		.WR_DATA(wr_data),
		.BYTE_SELECT(wr_bs),
		.ARST(arst)
	);
endmodule

[KrystalDelusion]

I don't think there is a way to tell read_verilog not to elaborate the simulation model if it's provided. But also very large memories are not inherently problematic. Take this TDP model for example:
blockram.v

module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
   (input  wire                      clk_a, clk_b, 
    input  wire                      write_enable_a, write_enable_b,
    input  wire                      read_enable_a, read_enable_b,
    input  wire  [DATA_WIDTH-1:0]    write_data_a, write_data_b,
    input  wire  [ADDRESS_WIDTH-1:0] addr_a, addr_b,
    output reg   [DATA_WIDTH-1:0]    read_data_a, read_data_b);

  localparam WORD  = (DATA_WIDTH-1);
  localparam DEPTH = (2**ADDRESS_WIDTH-1);

  reg [WORD:0] mem [0:DEPTH];

  always @(posedge clk_a) begin
    if (write_enable_a)
      mem[addr_a] <= write_data_a;
    else
      read_data_a <= mem[addr_a];
  end

  always @(posedge clk_b) begin
    if (write_enable_b)
      mem[addr_b] <= write_data_b;
    else
      read_data_b <= mem[addr_b];
  end

endmodule // sync_ram_tdp

Running memory.ys

read_verilog -defer blockram.v
chparam -set ADDRESS_WIDTH 16 -set DATA_WIDTH 32 sync_ram_tdp
hierarchy -top sync_ram_tdp

Even with 64b x 32B that completes in under a second (mind you memories that large do crash in other places, but hierarchy is fine). Replacing hierarchy with synth_xilinx for a 16b x 4B memory (the same size you are using) will fully synthesize in ~2s on my system.

The major problem here is that read_verilog does not like that memory model, I think specifically because of the always @(*). As soon as there is more than one edge event (always @(clk), always @(posedge clk, posedge arst)) then read_verilog will convert the memory to a list of registers.

I don't think there is any way to do an asynchronous full memory reset in Yosys (and honestly even a synchronous full memory reset would probably cause issues in memory), but for a configurable polarity/enable you would typically have extra signals and do something like:

wire clk_r = RD_CLK_POLARITY ? RD_CLK : ~RD_CLK;
wire en_r = RD_CLK_ENABLE ? RD_EN : 1'b1;
always @(posedge clk_r) begin
  if (en_r) begin
    // ..
  end
end

[KrystalDelusion]

Also FYI that the Yosys Discourse is the preferred place to ask questions like this :)