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483 Open 1,397 Closed
483 Open 1,397 Closed
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Issues list

Multiple edge sensitive events found for this signal! pending-verification This issue is pending verification and/or reproduction
#5079 opened Apr 30, 2025 by lovisXII
1
Flag to avoid writing Yosys version numbers into AIG files. feature-request
#5077 opened Apr 29, 2025 by dinoruic
@widlarizer
1
Parsing very long strings with read_verilog is much slower than alternatives pending-verification This issue is pending verification and/or reproduction
#5076 opened Apr 29, 2025 by rroohhh
1
CXXRTL: Missing sign extension before shift operation for signed values bug cxxrtl
#5074 opened Apr 29, 2025 by sdjasj
1
2
sim: run_cosim_fst leaks memory bug
#5071 opened Apr 28, 2025 by widlarizer
read_verilog: empty parameter value leaks memory bug SystemVerilog Issues and questions related to SystemVerilog
#5069 opened Apr 28, 2025 by widlarizer
2
DSP pmg passes have unsound sign extension logic pending-verification This issue is pending verification and/or reproduction
#5059 opened Apr 23, 2025 by widlarizer
@widlarizer
The value<N> in CXXRTL does not automatically truncate the value to fit within the bit-width range. cxxrtl Fuzzer Fuzzer generated issue
#5042 opened Apr 19, 2025 by sdjasj
3
Failure when building Yosys pending-verification This issue is pending verification and/or reproduction
#5038 opened Apr 17, 2025 by eder-matheus
3
Wide mux cells ($_MUX4_ et al) are incorrectly marked as evaluable
#5035 opened Apr 16, 2025 by KrystalDelusion
1
failure in yosys-abc with return code 134 ABC bug liberty Issues to do with Liberty files
#5028 opened Apr 16, 2025 by Cronus-38
2
Add support for mapping arrays with global reset to memory_map
#5022 opened Apr 14, 2025 by nakengelhardt
@jix
AddressSanitizer issues pending-verification This issue is pending verification and/or reproduction
#5020 opened Apr 11, 2025 by KrystalDelusion
equiv_opt falsely claims equivalence on designs with different unknown modules bug
#5018 opened Apr 11, 2025 by widlarizer
@widlarizer
fsm_expand deleting design if state register is not initialised bug
#5014 opened Apr 10, 2025 by KelvinChung2000
2
opt_mem pass is not respecting (* keep *) bug
#5010 opened Apr 9, 2025 by KelvinChung2000
1
Add annotations in CI for warnings in tests feature-request
#5007 opened Apr 9, 2025 by KrystalDelusion
Script errors should give a line number feature-request
#5006 opened Apr 9, 2025 by KrystalDelusion
Possible memory leak at CHECK pass needs-info Issue needs more context/information in order to be resolved pending-verification This issue is pending verification and/or reproduction
#5002 opened Apr 8, 2025 by RicardoLera
3
ANSI-style modules from write_verilog feature-request
#4993 opened Apr 6, 2025 by oscargus
ERROR: Assert sig_macc.count(n->y) == 0 failed occurs when multiple $add cells drive the same signal. error handling Error handling and reporting Fuzzer Fuzzer generated issue
#4991 opened Apr 5, 2025 by sdjasj
3
Support wildcards across Liberty file consumers feature-request
#4990 opened Apr 4, 2025 by widlarizer
@widlarizer
Inconsistent 'x handling in opt_expr for muxes pending-verification This issue is pending verification and/or reproduction
#4988 opened Apr 3, 2025 by KrystalDelusion
ERROR: Assert 'signal_list[id1].bit.wire != nullptr' occurred during the synth_efinix Fuzzer Fuzzer generated issue pending-verification This issue is pending verification and/or reproduction
#4987 opened Apr 3, 2025 by sdjasj
9
A core dumped occurred during the synth_microchip process when executing the MICROCHIP_DSP pass. Fuzzer Fuzzer generated issue pending-verification This issue is pending verification and/or reproduction
#4985 opened Apr 3, 2025 by sdjasj
3
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