Setting up Yosys for an ASIC with power ports

[svenboulanger]

I would like to add explicit power ports to the Spice netlist that comes out of Yosys for ASIC designs, but I am having difficulties figuring out a way to do so. Relying on global nets is not possible due to the larger design having multiple power supplies. Also, some cells have an additional power port other than just VDD/VSS.

I've figured out in the meantime that I can specify power ports in a Verilog file and read the netlist using the -lib flag, but all the power pins are unconnected when I write the Spice file with write_spice. I tried to manually make connections through the connect statement, but I couldn't find a way to call the connect -port command on all selected cells.

Is there a way to have explicit power ports with Yosys, or do I have to write an extra tool that reads the exported netlist and adds the power ports?