Creating a scan chain

[Topi-ab]

For sw-hw co-emulation tryout, I need to automatically create scan-chain to custom dff:s. Target is fpga.

I managed to tech-map all dff:s with a custom one, now I need to daisy-chain them, i.e. connecting scan-input of each ff to output of previous-in-chain.

Any ideas how to automate it?

[stdefeber]

Scan chains are to my humble opinion never used on FPGA's. Why do you want it ?

With some elbow grease and a python script they can be logically connected.

However, during place and route, at least in the ASIC world, scan chains will be reordered depending on placement optimization.
Some more questions to consider:

• are separate pins available for primary inputs/outputs ? If not you need to mux them with functional pins. Which adds additional logic.
• how many scan chains do you need ?
• is compression required ?

[whitequark]

Scan chains are to my humble opinion never used on FPGA's. Why do you want it ?

There is a valid reason to use scan chains on an FPGA: state readout on devices without native support.

[Topi-ab]

I am building FPGA based RTL emulator, and need to chain the internal state out for SW needs.

I found pyosys, which is exactly what I needed. Managed to create proof of concept:

https://github.com/Topi-ab/pyosys_scan_chain

[stdefeber]

There is a valid reason to use scan chains on an FPGA: state readout on devices without native support.

Great use indeed.