How to write an aiger file with blockboxes ?

[stdefeber]

Hi all,

I am working on a Yosys flow similar in spirit to #5067 , but with a slightly different goal.

After running alumacc, I would like to:

• Identify “coarse” arithmetic modules (e.g. $alu, $add, $mul, $macc, etc.)
• Blackbox only these modules
• Convert the remaining logic to AIGER, while keeping the blackboxes

Is there a recommended way to reliably identify modules after alumacc and blackbox them?

I am experimenting with a comparator.

module comparator #(
    parameter WIDTH = 8
)(
    input  wire [WIDTH-1:0] A,
    input  wire [WIDTH-1:0] B,
    output wire eq,
    output wire lt,
    output wire gt
);

  assign eq = (A == B);
  assign lt = (A <  B);
  assign gt = (A >  B);

endmodule

read_verilog comparator.v
hierarchy -check -top comparator
proc; wreduce; alumacc; opt

# 1. Identify de ALU
rename -enumerate -pattern MY_ALU_% t:$alu

# 2. Write metadata
write_json comparator.json

# 3. Isolate MY_ALU* ports
# Split buses into wires
splitnets -ports c:MY_ALU_*
# Treat MY_ALU* ports as IO
expose -shared c:MY_ALU_*

# 4. Remove the ALU
# Keep the ports of the ALU
delete c:MY_ALU_*

# 5. Clean-up
techmap; opt
abc -g AND
opt -purge

# 6. Write AIGER
write_aiger -zinit -symbols comparator.aig

Graphical representation of the json file after netlistsvg:

The error it throws is:

7. Executing AIGER backend.
ERROR: Unsupported cell type: $alu (MY_ALU_0)

Trying the blackbox option:

read_verilog comparator.v
hierarchy -check -top comparator
proc; wreduce; alumacc; opt
rename -enumerate -pattern MY_ALU_% t:$alu
blackbox c:MY_ALU_*
setattr -set keep 1 c:MY_ALU_*
write_json comparator.json
splitnets -ports
techmap; opt
abc -g AND
write_aiger -zinit -symbols comparator.aig

Altough this produces an aiger file, the ALU is not blackboxed.

Any guidance, best practices, or example flows would be greatly appreciated.

Best regards,

Simon