This repository contains the complete design flow for a Half Adder, starting from schematic creation to GDSII generation, using Cadence tools with the GPDK90 process library. A half adder is a fundamental digital circuit that performs binary addition on two single-bit inputs, generating a sum and a carry output. This project covers schematic design, layout, design rule checks (DRC), layout versus schematic checks (LVS), and RC extraction.
A half adder is a combinational circuit that adds two single-bit binary numbers (A and B). It produces two outputs:
- Sum (S): Result of the binary addition.
- Carry (C): Represents any overflow into the next higher bit.
Truth Table:
| Input A | Input B | Sum (S) | Carry (C) |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
This project follows a standard ASIC design flow for digital circuits:
- Schematic Creation
- Symbol and Testbench Setup
- Pre-Layout Simulation
- Layout Creation (DRC and LVS checks)
- Post-Layout Simulation
- RC Extraction
- GDSII Generation
The initial schematic of the Half Adder was created using GPDK90 in Cadence. The schematic forms the base for further simulations and layout design.
Schematic Diagram:
A symbol view was generated for the Half Adder, and a testbench was set up to verify its functionality through transient and delay analysis.
Symbol and Testbench:
Simulations were run to verify the functionality and performance of the Half Adder. Critical parameters like delay from input A to Sum and Carry were analyzed.
Simulation Results (Pre-Layout):
Delay from Terminal 'A' to 'Sum':
Delay from Terminal 'A' to 'Carry':
The Half Adder layout was designed using Cadence Virtuoso with GPDK90. After completing the layout, Design Rule Check (DRC) and Layout Versus Schematic (LVS) checks were performed to ensure compliance and correctness.
DRC and LVS Checks:
- DRC: Passed successfully
- LVS: Passed successfully
DRC Result:
LVS Result:
After layout, post-layout simulations were conducted to examine performance changes due to parasitic elements. Delays from terminal A to Sum and Carry were analyzed again.
Post-Layout Simulation Results:
Delay from Terminal 'A' to 'Sum':
Delay from Terminal 'A' to 'Carry':
RC extraction was performed to capture parasitic capacitance and resistance, ensuring post-layout simulations reflect realistic circuit behavior.
RC Extraction Results:
The final design was exported in GDSII format for tape-out or further processing steps.
GDSII Output:
- DRC (Design Rule Check): Ensures that the layout complies with specific design rules set by the fabrication process.
- LVS (Layout Versus Schematic): Verifies that the layout corresponds accurately to the schematic netlist.
- RC Extraction: Process of modeling parasitic resistances (R) and capacitances (C) after layout, which impact signal delay and power consumption.
- GDSII Format: A binary format for transferring IC layout data to silicon foundries.
- Cadence Virtuoso for Schematic, Layout, and GDSII generation
- Spectre Simulator for pre- and post-layout simulations
- GPDK90: A generic process design kit based on 90 nm technology
We gratefully acknowledge the support from the Chips to Startup (C2S) program, MeitY, Government of India, provided to Aligarh Muslim University, which enabled us to access industry-standard tools and training resources. We also extend our sincere gratitude to our course instructor for their invaluable guidance throughout this project. This work is part of the Digital IC Design course in Semester 7 of the B.Tech Electronics Engineering program at Aligarh Muslim University.