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auto offloading in dynamic shape IR #1313

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auto offloading in dynamic shape IR #1313

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0ee3b55
init auto remat(offloading) in dynamic shape graph
Yancey1989 Aug 19, 2024
6bd9ec4
update
Yancey1989 Aug 19, 2024
6d6a1d5
update
Yancey1989 Aug 19, 2024
f610ff7
init async offloading
Yancey1989 Aug 28, 2024
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31 changes: 30 additions & 1 deletion tao_compiler/mlir/disc/BUILD
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Original file line number Diff line number Diff line change
Expand Up @@ -341,6 +341,7 @@ cc_library(
":codegen_utils",
":disc_shape_optimization_utils",
":disc_util",
":disc_offloading",
"@org_tensorflow//tensorflow/compiler/xla/mlir_hlo:mlir_hlo",
"@org_tensorflow//tensorflow/compiler/xla/mlir_hlo:lhlo",
"@org_tensorflow//tensorflow/compiler/xla/mlir_hlo:map_lmhlo_to_scalar_op",
Expand Down Expand Up @@ -2228,7 +2229,35 @@ cc_library(
],
alwayslink = 1,
)

cc_library(
name = "disc_offloading",
srcs = [
"transforms/disc_dynamic_offloading.cc",
"transforms/disc_remat_utils.cc"
],
hdrs = [
"transforms/passes.h",
"transforms/disc_remat_utils.h"
],
includes = ["include"],
deps = [
":disc_ral",
":disc_util",
":mhlo_disc",
":pass_details",
":shape_utils",
"@org_tensorflow//tensorflow/compiler/xla/mlir_hlo:mlir_hlo",
"@org_tensorflow//tensorflow/compiler/xla/mlir_hlo:lhlo",
"@org_tensorflow//tensorflow/compiler/xla/mlir_hlo:map_lmhlo_to_scalar_op",
"@llvm-project//llvm:Support",
"@llvm-project//mlir:GPUDialect",
"@llvm-project//mlir:IR",
"@llvm-project//mlir:MemRefDialect",
"@llvm-project//mlir:Pass",
"@llvm-project//mlir:SCFDialect",
"@llvm-project//mlir:Transforms",
]
)
cc_library(
name = "disc_custom_call_rewriter",
srcs = ["transforms/disc_custom_call_rewriter.cc"],
Expand Down
14 changes: 7 additions & 7 deletions tao_compiler/mlir/disc/disc_compiler.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -242,10 +242,9 @@ LogicalResult LowerHLOToLLVM(ModuleOp m, const DISCLoweringOptions& options) {
/*printModuleScope=*/false,
/*printAfterOnlyOnChange=*/true,
/*printAfterOnlyOnFailure*/ false, llvm::dbgs(), printingFlags);

pm.addPass(disc_ral::createDiscShapePropagatePass());
pm.addNestedPass<FuncOp>(disc_ral::createDiscAlgebraicSimplifierPass());
pm.addPass(disc_ral::createDiscInputOutputAliasPass());
pm.addPass(disc_ral::createDiscShapePropagatePass());
pm.addPass(mlir::createInlinerPass());
// TODO(disc): Lower HLO shape constraints instead of eliding them here.
pm.addNestedPass<FuncOp>(disc_ral::createDiscCollectiveOpsRewriterPass());
Expand All @@ -269,8 +268,8 @@ LogicalResult LowerHLOToLLVM(ModuleOp m, const DISCLoweringOptions& options) {
pm.addNestedPass<FuncOp>(
disc_ral::createDiscLowerQuantizeAndDequantizePass());
}

bool enable_shape_constraint_ir = useShapeConstraintIR();

if (!enable_shape_constraint_ir) {
// propagate some known shape information.
pm.addPass(disc_ral::createDiscShapeSimplifierPass());
Expand All @@ -279,7 +278,6 @@ LogicalResult LowerHLOToLLVM(ModuleOp m, const DISCLoweringOptions& options) {
// shape-related optimization
pm.addPass(disc_ral::createDiscShapeOptimizationPass());
}

pm.addNestedPass<FuncOp>(disc_ral::createDiscConvertTensorToStandardPass());
pm.addNestedPass<FuncOp>(disc_ral::createDiscConvertHloToStandardPass());
pm.addNestedPass<FuncOp>(createCanonicalizerPass());
Expand Down Expand Up @@ -500,9 +498,9 @@ LogicalResult LowerHLOToLLVM(ModuleOp m, const DISCLoweringOptions& options) {
if (gpu_enabled) {
// TODO: Support cpu stitch with splat const
pm.addNestedPass<FuncOp>(disc_ral::createDiscFuseSplatConstPass());
pm.addNestedPass<FuncOp>(
disc_ral::createDiscSpecializeFusionWithSpeculationPass(
gpu_options.sm_count, gpu_options.max_threads_per_sm));
// pm.addNestedPass<FuncOp>(
// disc_ral::createDiscSpecializeFusionWithSpeculationPass(
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Any problems with it?

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just easier to analysis buffer living range, will remove this comment.

// gpu_options.sm_count, gpu_options.max_threads_per_sm));
} else {
pm.addNestedPass<FuncOp>(
disc_ral::createDiscDuplicateComputationAfterFusionPass());
Expand Down Expand Up @@ -545,6 +543,8 @@ LogicalResult LowerHLOToLLVM(ModuleOp m, const DISCLoweringOptions& options) {
pm.addNestedPass<FuncOp>(disc_ral::createDiscBufferDeallocationPass());

pm.addPass(disc_ral::createRalInjectExecutionContextPass());
// pm.addPass(mhlo_disc::createDiscArgsMutationExpandPass());
// pm.addNestedPass<FuncOp>(disc_ral::createDiscOffloadingPass());
pm.addNestedPass<FuncOp>(
disc_ral::createDiscLowerToLibraryCallPass(gpu_enabled));
pm.addPass(disc_ral::createDiscConstToRALPass(options.metadata_file_path));
Expand Down
2 changes: 2 additions & 0 deletions tao_compiler/mlir/disc/disc_compiler_main.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -210,11 +210,13 @@ int RealMain() {
<< " s.\n";

llvm::dbgs() << "[[ INFO ]] Running TF2XLA\n";
/*
auto s = tensorflow::ConvertTF2MlirHlo(module);
if (!s.ok()) {
llvm::dbgs() << "ConvertTF2MlirHlo failed: " << s.ToString() << "\n";
return 1;
}
*/

if (VLOG_IS_ON(0)) {
llvm::dbgs() << "======== BEGIN After TF2HLO =========\n";
Expand Down
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