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added some op codes
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aowalke2 committed Mar 9, 2024
1 parent 82d2b6e commit 8ecc302
Showing 1 changed file with 99 additions and 6 deletions.
105 changes: 99 additions & 6 deletions src/cpu.rs
Original file line number Diff line number Diff line change
Expand Up @@ -89,6 +89,48 @@ impl Cpu {
self.program_counter = opcode & 0x0FFF;
}

fn se_vx_and_byte(&mut self, opcode: u16) {
let register = (opcode & 0x0F00) >> 8;
let data = self.registers[(register - 1) as usize];
if data == (opcode & 0x00FF) as u8 {
self.program_counter += 2;
}
}

fn sne_vx_and_byte(&mut self, opcode: u16) {
let register = (opcode & 0x0F00) >> 8;
let data = self.registers[(register - 1) as usize];
if data != (opcode & 0x00FF) as u8 {
self.program_counter += 2;
}
}

fn se_vx_and_vy(&mut self, opcode: u16) {
let register_x = (opcode & 0x0F00) >> 8;
let register_y = (opcode & 0x00F0) >> 4;
let data_x = self.registers[(register_x - 1) as usize];
let data_y = self.registers[(register_y - 1) as usize];
if data_x == data_y {
self.program_counter += 2;
}
}

fn ld_vx_with_byte(&mut self, opcode: u16) {
let register = (opcode & 0x0F00) >> 8;
self.registers[(register - 1) as usize] = (opcode & 0x00FF) as u8;
}

fn add_vx_with_byte(&mut self, opcode: u16) {
let register = (opcode & 0x0F00) >> 8;
self.registers[(register - 1) as usize] += (opcode & 0x00FF) as u8;
}

fn ld_vx_with_vy(&mut self, opcode: u16) {
let register_x = (opcode & 0x0F00) >> 8;
let register_y = (opcode & 0x00F0) >> 4;
self.registers[(register_x - 1) as usize] = self.registers[(register_y - 1) as usize];
}

pub fn tick_timers(&mut self) {
if self.delay_timer > 0 {
self.delay_timer -= 1;
Expand Down Expand Up @@ -128,12 +170,12 @@ impl Cpu {
(0, 0, 0xE, 0xE) => self.ret(),
(1, _, _, _) => self.jp(opcode),
(2, _, _, _) => self.call(opcode),
(3, _, _, _) => println!("SE Vx, byte: {opcode}"),
(4, _, _, _) => println!("SNE Vx, byte: {opcode}"),
(5, _, _, _) => println!("SE Vx, Vy: {opcode}"),
(6, _, _, _) => println!("LD Vx, byte: {opcode}"),
(7, _, _, _) => println!("ADD Vx, byte: {opcode}"),
(8, _, _, 0) => println!("LD Vx, Vy: {opcode}"),
(3, _, _, _) => self.se_vx_and_byte(opcode),
(4, _, _, _) => self.sne_vx_and_byte(opcode),
(5, _, _, _) => self.se_vx_and_vy(opcode),
(6, _, _, _) => self.ld_vx_with_byte(opcode),
(7, _, _, _) => self.add_vx_with_byte(opcode),
(8, _, _, 0) => self.ld_vx_with_vy(opcode),
(8, _, _, 1) => println!("OR Vx, Vy: {opcode}"),
(8, _, _, 2) => println!("AND Vx, Vy: {opcode}"),
(8, _, _, 3) => println!("XOR Vx, Vy: {opcode}"),
Expand Down Expand Up @@ -221,4 +263,55 @@ mod test {
assert_eq!(cpu.stack_pop(), 0x0200);
assert_eq!(cpu.program_counter, 0x0222)
}

#[test]
fn test_se_vx_and_byte() {
let mut cpu = Cpu::new();
cpu.program_counter = PROGRAM_START;
cpu.registers[1] = 0x55;
cpu.se_vx_and_byte(0x3255);
assert_eq!(cpu.program_counter, 0x0202)
}

#[test]
fn test_sne_vx_and_byte() {
let mut cpu = Cpu::new();
cpu.program_counter = PROGRAM_START;
cpu.registers[1] = 0x55;
cpu.sne_vx_and_byte(0x4244);
assert_eq!(cpu.program_counter, 0x0202)
}

#[test]
fn test_se_vx_and_vy() {
let mut cpu = Cpu::new();
cpu.program_counter = PROGRAM_START;
cpu.registers[1] = 0x55;
cpu.registers[2] = 0x55;
cpu.se_vx_and_vy(0x5230);
assert_eq!(cpu.program_counter, 0x0202)
}

#[test]
fn test_ld_vx_with_byte() {
let mut cpu = Cpu::new();
cpu.ld_vx_with_byte(0x6230);
assert_eq!(cpu.registers[1], 0x0030)
}

#[test]
fn test_add_vx_with_byte() {
let mut cpu = Cpu::new();
cpu.registers[1] = 0x33;
cpu.add_vx_with_byte(0x7230);
assert_eq!(cpu.registers[1], 0x0063)
}

#[test]
fn test_ld_vx_with_vy() {
let mut cpu = Cpu::new();
cpu.registers[2] = 0x33;
cpu.ld_vx_with_vy(0x8230);
assert_eq!(cpu.registers[1], 0x0033)
}
}

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