@@ -193,138 +193,109 @@ stm32_hw_setup(int num, TIM_TypeDef *regs)
193193
194194#ifdef TIM1
195195 if (regs == TIM1 ) {
196- #if MYNEWT_VAL (MCU_STM32F0 )
197- stm32_tmr_reg_irq (TIM1_CC_IRQn , func );
198- #elif MYNEWT_VAL (MCU_STM32F3 ) || MYNEWT_VAL (MCU_STM32L4 ) || MYNEWT_VAL (MCU_STM32WB )
199- stm32_tmr_reg_irq (TIM1_UP_TIM16_IRQn , func );
200- #elif MYNEWT_VAL (MCU_STM32U5 )
201- stm32_tmr_reg_irq (TIM1_UP_IRQn , func );
202- #else
203- stm32_tmr_reg_irq (TIM1_UP_TIM10_IRQn , func );
204- #endif
196+ stm32_tmr_reg_irq (STM32_HAL_TIMER_TIM1_IRQ , func );
205197 __HAL_RCC_TIM1_CLK_ENABLE ();
206198 }
207199#endif
208200#ifdef TIM2
209201 if (regs == TIM2 ) {
210- stm32_tmr_reg_irq (TIM2_IRQn , func );
202+ stm32_tmr_reg_irq (STM32_HAL_TIMER_TIM2_IRQ , func );
211203 __HAL_RCC_TIM2_CLK_ENABLE ();
212204 }
213205#endif
214206#ifdef TIM3
215207 if (regs == TIM3 ) {
216- stm32_tmr_reg_irq (TIM3_IRQn , func );
208+ stm32_tmr_reg_irq (STM32_HAL_TIMER_TIM3_IRQ , func );
217209 __HAL_RCC_TIM3_CLK_ENABLE ();
218210 }
219211#endif
220212#ifdef TIM4
221213 if (regs == TIM4 ) {
222- stm32_tmr_reg_irq (TIM4_IRQn , func );
214+ stm32_tmr_reg_irq (STM32_HAL_TIMER_TIM4_IRQ , func );
223215 __HAL_RCC_TIM4_CLK_ENABLE ();
224216 }
225217#endif
218+ #ifdef TIM6
219+ if (regs == TIM6 ) {
220+ stm32_tmr_reg_irq (STM32_HAL_TIMER_TIM6_IRQ , func );
221+ __HAL_RCC_TIM6_CLK_ENABLE ();
222+ }
223+ #endif
224+ #ifdef TIM7
225+ if (regs == TIM7 ) {
226+ stm32_tmr_reg_irq (STM32_HAL_TIMER_TIM7_IRQ , func );
227+ __HAL_RCC_TIM7_CLK_ENABLE ();
228+ }
229+ #endif
226230#ifdef TIM8
227231 if (regs == TIM8 ) {
228- stm32_tmr_reg_irq (TIM8_CC_IRQn , func );
229- #if MYNEWT_VAL (MCU_STM32F3 ) || MYNEWT_VAL (MCU_STM32L4 ) || MYNEWT_VAL (MCU_STM32WB ) || MYNEWT_VAL (MCU_STM32U5 )
230- stm32_tmr_reg_irq (TIM8_UP_IRQn , func );
231- #else
232- stm32_tmr_reg_irq (TIM8_UP_TIM13_IRQn , func );
233- #endif
232+ stm32_tmr_reg_irq (STM32_HAL_TIMER_TIM8_IRQ , func );
234233 __HAL_RCC_TIM8_CLK_ENABLE ();
235234 }
236235#endif
237236#ifdef TIM9
238237 if (regs == TIM9 ) {
239- #if MYNEWT_VAL (MCU_STM32L1 )
240- stm32_tmr_reg_irq (TIM9_IRQn , func );
241- #else
242- stm32_tmr_reg_irq (TIM1_BRK_TIM9_IRQn , func );
243- #endif
238+ stm32_tmr_reg_irq (STM32_HAL_TIMER_TIM9_IRQ , func );
244239 __HAL_RCC_TIM9_CLK_ENABLE ();
245240 }
246241#endif
247242#ifdef TIM10
248243 if (regs == TIM10 ) {
249- #if MYNEWT_VAL (MCU_STM32L1 ) || MYNEWT_VAL (MCU_STM32L4 ) || MYNEWT_VAL (MCU_STM32WB )
250- stm32_tmr_reg_irq (TIM10_IRQn , func );
251- #else
252- stm32_tmr_reg_irq (TIM1_UP_TIM10_IRQn , func );
253- #endif
244+ stm32_tmr_reg_irq (STM32_HAL_TIMER_TIM10_IRQ , func );
254245 __HAL_RCC_TIM10_CLK_ENABLE ();
255246 }
256247#endif
257248#ifdef TIM11
258249 if (regs == TIM11 ) {
259- #if MYNEWT_VAL (MCU_STM32L1 )
260- stm32_tmr_reg_irq (TIM11_IRQn , func );
261- #else
262- stm32_tmr_reg_irq (TIM1_TRG_COM_TIM11_IRQn , func );
263- #endif
250+ stm32_tmr_reg_irq (STM32_HAL_TIMER_TIM11_IRQ , func );
264251 __HAL_RCC_TIM11_CLK_ENABLE ();
265252 }
266253#endif
267254#ifdef TIM12
268255 if (regs == TIM12 ) {
269- stm32_tmr_reg_irq (TIM8_BRK_TIM12_IRQn , func );
256+ stm32_tmr_reg_irq (STM32_HAL_TIMER_TIM12_IRQ , func );
270257 __HAL_RCC_TIM12_CLK_ENABLE ();
271258 }
272259#endif
273260#ifdef TIM13
274261 if (regs == TIM13 ) {
275- stm32_tmr_reg_irq (TIM8_UP_TIM13_IRQn , func );
262+ stm32_tmr_reg_irq (STM32_HAL_TIMER_TIM13_IRQ , func );
276263 __HAL_RCC_TIM13_CLK_ENABLE ();
277264 }
278265#endif
279266#ifdef TIM14
280267 if (regs == TIM14 ) {
281- #if MYNEWT_VAL (MCU_STM32F0 )
282- stm32_tmr_reg_irq (TIM14_IRQn , func );
283- #else
284- stm32_tmr_reg_irq (TIM8_TRG_COM_TIM14_IRQn , func );
285- #endif
268+ stm32_tmr_reg_irq (STM32_HAL_TIMER_TIM14_IRQ , func );
286269 __HAL_RCC_TIM14_CLK_ENABLE ();
287270 }
288271#endif
289272#ifdef TIM15
290273 if (regs == TIM15 ) {
291- #if MYNEWT_VAL (MCU_STM32F0 ) || MYNEWT_VAL (MCU_STM32H7 ) || MYNEWT_VAL (MCU_STM32U5 )
292- stm32_tmr_reg_irq (TIM15_IRQn , func );
293- #else
294- stm32_tmr_reg_irq (TIM1_BRK_TIM15_IRQn , func );
295- #endif
274+ stm32_tmr_reg_irq (STM32_HAL_TIMER_TIM15_IRQ , func );
296275 __HAL_RCC_TIM15_CLK_ENABLE ();
297276 }
298277#endif
299278#ifdef TIM16
300279 if (regs == TIM16 ) {
301- #if MYNEWT_VAL (MCU_STM32F0 ) || MYNEWT_VAL (MCU_STM32H7 ) || MYNEWT_VAL (MCU_STM32U5 )
302- stm32_tmr_reg_irq (TIM16_IRQn , func );
303- #else
304- stm32_tmr_reg_irq (TIM1_UP_TIM16_IRQn , func );
305- #endif
280+ stm32_tmr_reg_irq (STM32_HAL_TIMER_TIM16_IRQ , func );
306281 __HAL_RCC_TIM16_CLK_ENABLE ();
307282 }
308283#endif
309284#ifdef TIM17
310285 if (regs == TIM17 ) {
311- #if MYNEWT_VAL (MCU_STM32F0 ) || MYNEWT_VAL (MCU_STM32H7 ) || MYNEWT_VAL (MCU_STM32U5 )
312- stm32_tmr_reg_irq (TIM17_IRQn , func );
313- #else
314- stm32_tmr_reg_irq (TIM1_TRG_COM_TIM17_IRQn , func );
315- #endif
286+ stm32_tmr_reg_irq (STM32_HAL_TIMER_TIM17_IRQ , func );
316287 __HAL_RCC_TIM17_CLK_ENABLE ();
317288 }
318289#endif
319290#ifdef TIM21
320291 if (regs == TIM21 ) {
321- stm32_tmr_reg_irq (TIM21_IRQn , func );
292+ stm32_tmr_reg_irq (STM32_HAL_TIMER_TIM21_IRQ , func );
322293 __HAL_RCC_TIM21_CLK_ENABLE ();
323294 }
324295#endif
325296#ifdef TIM22
326297 if (regs == TIM22 ) {
327- stm32_tmr_reg_irq (TIM22_IRQn , func );
298+ stm32_tmr_reg_irq (STM32_HAL_TIMER_TIM22_IRQ , func );
328299 __HAL_RCC_TIM22_CLK_ENABLE ();
329300 }
330301#endif
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