{bp-15318} use small lock in following files:

Documentation/platforms/arm/imx9/boards/imx95-evk/index.rst

@@ -0,0 +1,85 @@
+===============
+IMX95LPD5EVK-19
+===============
+
+The IMX95LPD5EVK-19 board is a platform designed to show the most commonly
+used features of the i.MX 95 automotive applications processor.
+
+Features
+========
+
+- Multicore Processing [1]_
+    - 1x Arm Cortex-M7
+    - 6x Arm Cortex-A55 multicore complex
+    - 1x Arm Cortex-M33
+- Memory
+    - On-Chip Memory
+        - 1376kB SRAM (ECC)
+    - External Memory
+        - Up to 6.4GT/s x32 LPDDR5/LPDDR4X (with Inline ECC & Inline Encrpytion)
+        - 1x Octal SPI, including support for SPI NOR and SPI NAND memories
+- Connectivity
+    - CAN FD
+    - UART/USART/Profibus, I²C, SPI
+    - Messaging Units (MU) to support IPC between heterogeneous cores
+
+.. [1] NuttX is currently supported exclusively on the Cortex-M7 core of the
+       i.MX95
+
+Serial Console
+==============
+
+The IMX95LPD5EVK-19 board features a high-speed USB-to-UART/MPSSE device,
+FT4232H (U70) that provides a debug interface for the i.MX95 processor through
+the USB type-C connector (J31). The device acts as a bridge to enable
+communication between the target processor and the host computer, which
+connects to the USB connector (J31) through a USB cable.
+
+Channel A is used as UART port to provide USB-to-UART option for debugging the
+Arm Cortex-M7 core of the i.MX 95 processor (default option).
+
+J-Link External Debug Probe
+===========================
+
+The IMX95LPD5EVK-19 board provides a 2x5-pin Samtec FTSH-105-01-L-DV-K header
+(J30) for connecting a JTAG debugger (external JTAG) for debugging the i.MX95
+processor. The FT4234H JTAG provides the remote debug option for the i.MX95
+processor.
+
+Configurations
+==============
+
+nsh
+---
+
+Configures the NuttShell (nsh) located at examples/nsh.  This NSH
+configuration is focused on low level, command-line driver testing. Built-in
+applications are supported, but none are enabled. This configuration does not
+support a network.
+
+This configuration can be used in combination with the default sd-card image
+that is shipped with the EVK.
+
+rpmsg
+-----
+
+This configuration is similar to nsh but in addition it offers the Remote
+Processing Messaging (RPMsg) service to enable heterogeneous inter-core
+communication. A virtual UART (CONFIG_RPMSG_UART) is made available on which
+an OS running on the A55 cores can connect. There is also an option to use
+the filesystem client feature in which a remote directory can be mounted to
+a local directory (CONFIG_FS_RPMSGFS).
+
+The rpmsg configuration executes the code from DDR since its code memory
+footprint is bigger than the ITCM size. In the case of using the default
+sd-card image from the EVK, adaptations are needed on the software running on
+the M33 and A55 cores.
+
+    - `System Manager <https://github.com/nxp-imx/imx-sm>`_ (M33) should give
+      the M7 access to the DDR region
+    - `linux-imx <https://github.com/nxp-imx/linux-imx>`_ (A55) should reserve
+      the DDR region by specifying it in the device tree so linux won't make
+      use of it
+    - `linux-imx <https://github.com/nxp-imx/linux-imx>`_ (A55) needs the
+      NuttX compatible rpmsg_tty and rpmsg_fs drivers. See `dev mailing list
+      <https://www.mail-archive.com/[email protected]/msg12112.html>`_

Documentation/platforms/arm/imx9/index.rst

@@ -0,0 +1,12 @@
+===================
+NXP i.MX9
+===================
+
+Supported Boards
+================
+
+.. toctree::
+   :glob:
+   :maxdepth: 1
+
+   boards/*/*

arch/arm/Kconfig

@@ -183,6 +183,20 @@ config ARCH_CHIP_IMX6
 	---help---
 		Freescale iMX.6 architectures (Cortex-A9)
 
+config ARCH_CHIP_IMX9_CORTEX_M
+	bool "NXP iMX.9 Cortex-M7"
+	select ARCH_CORTEXM7
+	select ARCH_HAVE_MPU
+	select ARCH_HAVE_FETCHADD
+	select ARCH_HAVE_RAMFUNCS
+	select ARCH_HAVE_TICKLESS
+	select ARCH_HAVE_I2CRESET
+	select ARCH_HAVE_SPI_CS_CONTROL
+	select ARM_HAVE_MPU_UNIFIED
+	select ARMV7M_HAVE_STACKCHECK
+	---help---
+		iMX.9 architectures (Cortex-M7)
+
 config ARCH_CHIP_IMXRT
 	bool "NXP/Freescale iMX.RT"
 	select ARCH_CORTEXM7
@@ -1124,6 +1138,7 @@ config ARCH_CHIP
 	default "gd32f4"	if ARCH_CHIP_GD32F4
 	default "imx1"		if ARCH_CHIP_IMX1
 	default "imx6"		if ARCH_CHIP_IMX6
+	default "imx9"		if ARCH_CHIP_IMX9_CORTEX_M
 	default "imxrt"		if ARCH_CHIP_IMXRT
 	default "kinetis"	if ARCH_CHIP_KINETIS
 	default "kl"		if ARCH_CHIP_KL
@@ -1536,6 +1551,9 @@ endif
 if ARCH_CHIP_IMX6
 source "arch/arm/src/imx6/Kconfig"
 endif
+if ARCH_CHIP_IMX9_CORTEX_M
+source "arch/arm/src/imx9/Kconfig"
+endif
 if ARCH_CHIP_IMXRT
 source "arch/arm/src/imxrt/Kconfig"
 endif

arch/arm/include/imx9/chip.h

@@ -0,0 +1,52 @@
+/****************************************************************************
+ * arch/arm/include/imx9/chip.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * SPDX-FileCopyrightText: 2024 NXP
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_IMX9_CHIP_H
+#define __ARCH_ARM_INCLUDE_IMX9_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* NVIC priority levels *****************************************************/
+
+/* Each priority field holds an 8-bit priority value, 0-15. The lower the
+ * value, the greater the priority of the corresponding interrupt.  The i.MX
+ * RT processor implements only bits[7:4] of each field, bits[3:0] read as
+ * zero and ignore writes.
+ */
+
+#define NVIC_SYSH_PRIORITY_MIN        0xf0 /* All bits[7:4] set is min pri */
+#define NVIC_SYSH_PRIORITY_DEFAULT    0x80 /* Midpoint is the default */
+#define NVIC_SYSH_PRIORITY_MAX        0x00 /* Zero is maximum priority */
+#define NVIC_SYSH_PRIORITY_STEP       0x40 /* Two bits of interrupt pri used */
+
+#define IMX9_GPIO_NPORTS          4
+
+#endif /* __ARCH_ARM_INCLUDE_IMX9_CHIP_H */