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arch/risc-v: inline up_cpu_index if RISCV_PERCPU_SCRATCH is not enabled #15381

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Dec 31, 2024
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arch/risc-v: inline up_cpu_index if RISCV_PERCPU_SCRATCH is not enabled #15381

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17 changes: 17 additions & 0 deletions arch/risc-v/include/irq.h
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Original file line number Diff line number Diff line change
Expand Up @@ -697,10 +697,27 @@ irqstate_t up_irq_enable(void);
* Description:
* Return the real core number regardless CONFIG_SMP setting
*
* When CONFIG_RISCV_PERCPU_SCRATCH is enabled, this uses the percpu
* scratch area to store the hart ID. This is needed when the CSR_MHARTID
* register may not contain the actual hart ID.
*
* When CONFIG_RISCV_PERCPU_SCRATCH is not enabled, this directly reads
* the CSR_MHARTID register. Use this version when you can guarantee
* CSR_MHARTID contains the actual hart ID. This is the default behavior
* that can be achieved by single instruction to provide better
* performance.
*
****************************************************************************/

#ifdef CONFIG_ARCH_HAVE_MULTICPU
#ifdef CONFIG_RISCV_PERCPU_SCRATCH
int up_cpu_index(void) noinstrument_function;
#else
noinstrument_function static inline int up_cpu_index(void)
{
return READ_CSR(CSR_MHARTID);
}
#endif
#endif /* CONFIG_ARCH_HAVE_MULTICPU */

/****************************************************************************
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2 changes: 2 additions & 0 deletions arch/risc-v/src/common/riscv_cpuindex.c
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Expand Up @@ -45,10 +45,12 @@
*
****************************************************************************/

#ifdef CONFIG_RISCV_PERCPU_SCRATCH
int up_cpu_index(void)
{
return (int)riscv_mhartid();
}
#endif

/****************************************************************************
* Name: up_this_cpu
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