v1.0.1

Minor release - after flashing 50 Tiliquas, I discovered some PLLs lock a bit slower than others, which caused more video glitches when switching bitstreams. This release fixes this by always holding the DVI PLL in reset across switches, and also improves timing a bit along the way.

What's Changed

• timing/bootloader: cut timing, reduce bitstream switching video glitches by @vk2seb in #139
• bootloader/tiliqua_soc: fix dangling fb.enable reset after adding PLL reset (505dcae)

Note: On the first 50 units I only re-flashed the bootloader as that is where these changes actually make a difference, so some have bootloader v1.0.1 and user bitstreams v1.0.0.

Attached are all bitstreams built for all existing hardware platforms. plus a bonus one that wasn't quite ready to merge yet

Full Changelog: v1.0.0...v1.0.1

v1.0.0

First 'production' release (this suite of bitstreams will be flashed to CS R5 Tiliquas). Includes built-in help pages on most SoC bitstreams.

I was tempted to call this v0.1.0, but given that from this release onward, it will be important to track breaking changes in the bootloader / manifest system per semantic versioning, it's probably best to start with v1.0.0 and bump the major version on any breaking manifest / bootloader changes.

Attached are all bitstreams built for all existing hardware platforms. _{^{plus a bonus one that wasn't quite ready to merge yet}}