boards/tiliqua: add Tiliqua R2 as supported target

gateware/Makefile

@@ -15,7 +15,7 @@ ifeq ($(BOARD),)
 	@echo "For example:"
 	@echo "  $$ make clean"
 	@echo "  $$ # Build bitstream with specific core and program it"
-	@echo "  $$ make HW_REV=HW_R33 BOARD=icebreaker CORE=stereo_echo prog"
+	@echo "  $$ make HW_REV=HW_R33 BOARD=icebreaker CORE=mirror prog"
 	@exit 1
 endif
 ifeq ($(wildcard ./boards/$(BOARD)/Makefile),)

gateware/boards/colorlight_i5/Makefile

@@ -4,7 +4,8 @@ DEVICE = 25k
 PACKAGE = CABGA381
 SPEEDGRADE = 6
 PIN_DEF = ./boards/colorlight_i5/pinmap.lpf
-ADD_DEFINES = -DSELECTED_DSP_CORE=$(CORE)
+# UART: 1Mbaud
+ADD_DEFINES = -DSELECTED_DSP_CORE=$(CORE) -DDEBUG_UART_CLKDIV=12
 
 include ./mk/common.mk
 include ./mk/ecp5.mk

gateware/boards/colorlight_i9/Makefile

@@ -4,7 +4,8 @@ DEVICE = 45k
 PACKAGE = CABGA381
 SPEEDGRADE = 6
 PIN_DEF = ./boards/colorlight_i9/pinmap.lpf
-ADD_DEFINES = -DSELECTED_DSP_CORE=$(CORE)
+# UART: 1Mbaud
+ADD_DEFINES = -DSELECTED_DSP_CORE=$(CORE) -DDEBUG_UART_CLKDIV=12
 
 include ./mk/common.mk
 include ./mk/ecp5.mk

gateware/boards/ecpix5/Makefile

@@ -4,7 +4,8 @@ DEVICE = um5g-85k
 PACKAGE = CABGA554
 SPEEDGRADE = 8
 PIN_DEF = ./boards/ecpix5/pinmap.lpf
-ADD_DEFINES = -DSELECTED_DSP_CORE=$(CORE) -DINVERT_BUTTON=1
+# UART: 1Mbaud
+ADD_DEFINES = -DSELECTED_DSP_CORE=$(CORE) -DINVERT_BUTTON=1 -DDEBUG_UART_CLKDIV=12
 
 include ./mk/common.mk
 include ./mk/ecp5.mk

gateware/boards/gatemate_evb/Makefile

@@ -1,7 +1,8 @@
 PROJ = top
 
 PIN_DEF = ./boards/gatemate_evb/pinmap.ccf
-ADD_DEFINES = -DSELECTED_DSP_CORE=$(CORE) -DINVERT_BUTTON=1
+# UART: 1Mbaud
+ADD_DEFINES = -DSELECTED_DSP_CORE=$(CORE) -DINVERT_BUTTON=1 -DDEBUG_UART_CLKDIV=12
 
 include ./mk/common.mk
 include ./mk/gatemate.mk

gateware/boards/icebreaker/Makefile

@@ -3,7 +3,8 @@ PROJ = top
 DEVICE = up5k
 PACKAGE = sg48
 PIN_DEF = ./boards/icebreaker/pinmap.pcf
-ADD_DEFINES = -DSELECTED_DSP_CORE=$(CORE) -DINVERT_BUTTON=1
+# UART: 1Mbaud
+ADD_DEFINES = -DSELECTED_DSP_CORE=$(CORE) -DINVERT_BUTTON=1 -DDEBUG_UART_CLKDIV=12
 
 include ./mk/common.mk
 include ./mk/ice40.mk

gateware/boards/pico_ice/Makefile

@@ -3,7 +3,9 @@ PROJ = top
 DEVICE = up5k
 PACKAGE = sg48
 PIN_DEF = ./boards/pico_ice/pinmap.pcf
-ADD_DEFINES = -DSELECTED_DSP_CORE=$(CORE) -DINVERT_BUTTON=1 -DINTERNAL_CLOCK=1
+
+# UART: 115200 baud as RP2040 CDC converter assumes this.
+ADD_DEFINES = -DSELECTED_DSP_CORE=$(CORE) -DINVERT_BUTTON=1 -DINTERNAL_CLOCK=1 -DDEBUG_UART_CLKDIV=104
 
 include ./mk/common.mk
 include ./mk/ice40.mk

gateware/boards/tiliqua/Makefile

@@ -0,0 +1,17 @@
+PROJ = top
+
+DEVICE = 45k
+PACKAGE = CABGA256
+SPEEDGRADE = 7
+PIN_DEF = ./boards/tiliqua/pinmap.lpf
+# UART: 115200 baud as RP2040 CDC converter assumes this.
+ADD_DEFINES = -DSELECTED_DSP_CORE=$(CORE) -DINVERT_BUTTON=1 -DDEBUG_UART_CLKDIV=104
+
+include ./mk/common.mk
+include ./mk/ecp5.mk
+
+ADD_SRC = boards/tiliqua/sysmgr.v \
+		  $(SRC_COMMON)
+
+prog: $(BUILD)/$(PROJ).bin
+	openFPGALoader -c dirtyJtag $(BUILD)/$(PROJ).bin

gateware/boards/tiliqua/pinmap.lpf

@@ -0,0 +1,32 @@
+SYSCONFIG COMPRESS_CONFIG=ON;
+
+LOCATE      COMP "CLK" SITE "A8";
+IOBUF       PORT "CLK" IO_TYPE=LVCMOS33;
+FREQUENCY   PORT "CLK" 48 MHZ;
+
+# These pads are to the eurorack-pmod 'backpack' FFC.
+LOCATE COMP "PMOD_MCLK"    SITE "B11";
+LOCATE COMP "PMOD_PDN"     SITE "C11";
+LOCATE COMP "PMOD_I2C_SDA" SITE "D13";
+LOCATE COMP "PMOD_I2C_SCL" SITE "C13";
+LOCATE COMP "PMOD_SDIN1"   SITE "D8";
+LOCATE COMP "PMOD_SDOUT1"  SITE "C9";
+LOCATE COMP "PMOD_LRCK"    SITE "C10";
+LOCATE COMP "PMOD_BICK"    SITE "D9";
+
+IOBUF  PORT "PMOD_MCLK" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "PMOD_PDN" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "PMOD_I2C_SDA" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "PMOD_I2C_SCL" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "PMOD_SDIN1" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "PMOD_SDOUT1" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "PMOD_LRCK" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "PMOD_BICK" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+
+# This is the Tiliqua encoder switch.
+LOCATE COMP "RESET_BUTTON" SITE "D7";
+IOBUF  PORT "RESET_BUTTON" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;
+
+# This is connected to the Tiliqua RP2040 debugger.
+LOCATE COMP "UART_TX" SITE "B4";
+IOBUF  PORT "UART_TX" PULLMODE=NONE IO_TYPE=LVCMOS33 DRIVE=4;

gateware/boards/tiliqua/sysmgr.v

@@ -0,0 +1,71 @@
+`default_nettype none
+
+module sysmgr (
+    // Assumed 48Mhz for Tiliqua / Soldiercrab R2.0.
+	input  wire clk_in,
+	input  wire rst_in,
+	output wire clk_256fs,
+	output wire rst_out
+);
+
+wire clk_fb;
+wire pll_lock;
+wire pll_reset;
+wire rst_i;
+
+reg [7:0] rst_cnt;
+
+assign pll_reset = rst_in;
+assign rst_i = ~rst_cnt[7];
+assign rst_out = rst_i;
+
+`ifndef VERILATOR_LINT_ONLY
+
+// You can re-generate this using `ecppll` tool. Be careful, the default settings
+// disable PLLRST_ENA and use a different FEEDBK_PATH, make sure they remain.
+
+(* FREQUENCY_PIN_CLKI="25" *)
+(* FREQUENCY_PIN_CLKOS="12" *)
+(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
+EHXPLLL #(
+        .PLLRST_ENA("ENABLED"),
+        .INTFB_WAKE("DISABLED"),
+        .STDBY_ENABLE("DISABLED"),
+        .DPHASE_SOURCE("DISABLED"),
+        .OUTDIVIDER_MUXA("DIVA"),
+        .OUTDIVIDER_MUXB("DIVB"),
+        .OUTDIVIDER_MUXC("DIVC"),
+        .OUTDIVIDER_MUXD("DIVD"),
+        .CLKI_DIV(4),
+        .CLKOP_ENABLE("ENABLED"),
+        .CLKOP_DIV(50),
+        .CLKOP_CPHASE(24),
+        .CLKOP_FPHASE(0),
+        .FEEDBK_PATH("CLKOP"),
+        .CLKFB_DIV(1)
+) pll_i (
+        .RST(pll_reset),
+        .STDBY(1'b0),
+        .CLKI(clk_in),
+        .CLKOP(clk_256fs),
+        .CLKFB(clk_256fs),
+        .CLKINTFB(),
+        .PHASESEL0(1'b0),
+        .PHASESEL1(1'b0),
+        .PHASEDIR(1'b1),
+        .PHASESTEP(1'b1),
+        .PHASELOADREG(1'b1),
+        .PLLWAKESYNC(1'b0),
+        .ENCLKOP(1'b0),
+        .LOCK(pll_lock)
+);
+
+`endif
+
+always @(posedge clk_in)
+    if (!pll_lock)
+        rst_cnt <= 8'h0;
+    else if (~rst_cnt[7])
+        rst_cnt <= rst_cnt + 1;
+
+endmodule // sysmgr

gateware/cal/cal.py

@@ -251,7 +251,8 @@ def parse_args_with_defaults(defaults):
     args = CalibrationArguments()
     args = parse_args_with_defaults(args)
     if args.serial_port == "":
-        print("Nominal usage: ./cal.py --serial-port /dev/ttyUSBX")
+        print("Nominal usage: ./cal.py --serial-port /dev/ttyUSBX --serial-baud 1000000")
+        print("Warn: most boards are 1MBaud, check their Makefile to be sure!")
         sys.exit(0)  # Exit the program
     calibration_tool = CalibrationTool(args)
     calibration_tool.run_calibration()

gateware/top.sv

@@ -210,7 +210,7 @@ eurorack_pmod #(
 // for bringup and calibration purposes.
 debug_uart #(
     .W(W),
-    .DIV(12) // WARN: baud rate is determined by clk_256fs / 12 !!
+    .DIV(`DEBUG_UART_CLKDIV) // WARN: baud rate is determined by clk_256fs / CLKDIV !!
 ) debug_uart_instance (
     .clk (clk_256fs),
     .rst (rst),