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Avoid egde cases e.g. wrong masks for odd subnodes + new overlap case
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* avoid egde cases e.g. wrong masks and start node for odd subnodes + overlap warn of 32-bit data

* add comments to xml_generage.py + resolve clkr0a overlap in YML

* add clkmon and overlapped mask constraints to script

* a bit clean up
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pkotamnives authored Feb 3, 2024
1 parent 194f547 commit fcbbe14
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Showing 2 changed files with 78 additions and 37 deletions.
29 changes: 15 additions & 14 deletions data/PL_MEM_CM_rev2.yml
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ revision: 1
config:
- name: firefly
start: 0
count: 40
count: 60
mcu_call: firefly_info
mcu_extra_call: null
type: uint16_t
Expand Down Expand Up @@ -37,8 +37,9 @@ config:
postfixes:
- Temp_C
- OptPow
- TxDisabled
- name: uptime
start: 44
start: 60
count: 2
type: uint32_t
mcu_call: uptime
Expand All @@ -47,7 +48,7 @@ config:
names:
- MCU_UPTIME
- name: psmon
start: 47
start: 62
count: 84
mcu_call: psmon
mcu_extra_call: null
Expand Down Expand Up @@ -76,7 +77,7 @@ config:
- IOUT
- STATUS_WORD
- name: gitversion
start: 132
start: 146
count: 10
type: char
size: 5
Expand All @@ -85,7 +86,7 @@ config:
names:
- MCU_FW_VER
- name: adcmon
start: 143
start: 156
count: 21
mcu_call: adcmon
mcu_extra_call: null
Expand Down Expand Up @@ -114,7 +115,7 @@ config:
- F2_TEMP
- TM4C_TEMP
- name: fpga
start: 165
start: 177
count: 8
type: fp16
extra: Table=CM_MON;Column=Temp_C;Status=2;
Expand All @@ -130,7 +131,7 @@ config:
- F2_TEMP_SLR2
- F2_TEMP_SLR3
- name: clkmonr0a
start: 174
start: 186
count: 8
type: uint16_t
extra: Table=CM_CLK_MON;Status=1
Expand All @@ -148,7 +149,7 @@ config:
- LOSIN_FLG_OR_LOL
- STICKY_FLG
- name: clkmon
start: 182
start: 194
count: 32
type: uint16_t
extra: Table=CM_CLK_MON;Status=1
Expand All @@ -169,7 +170,7 @@ config:
- LOSIN_FLG_OR_LOL
- STICKY_FLG
- name: clkr0aconfigversion
start: 216
start: 228
count: 4
type: char
size: 2
Expand All @@ -178,7 +179,7 @@ config:
names:
- MCU_CLKR0A_VER
- name: clkr0bconfigversion
start: 220
start: 233
count: 4
type: char
size: 2
Expand All @@ -187,7 +188,7 @@ config:
names:
- MCU_CLKR0B_VER
- name: clkr1aconfigversion
start: 224
start: 238
count: 4
type: char
size: 2
Expand All @@ -196,7 +197,7 @@ config:
names:
- MCU_CLKR1A_VER
- name: clkr1bconfigversion
start: 228
start: 243
count: 4
type: char
size: 2
Expand All @@ -205,7 +206,7 @@ config:
names:
- MCU_CLKR1B_VER
- name: clkr1cconfigversion
start: 232
start: 248
count: 4
type: char
size: 2
Expand All @@ -214,7 +215,7 @@ config:
names:
- MCU_CLKR1C_VER
- name: firefly_bits
start: 236
start: 253
count: 8
type: uint16_t
extra: Table=CM_FFARGV_MON;Status=1
Expand Down
86 changes: 63 additions & 23 deletions src/xml_generate.py
Original file line number Diff line number Diff line change
@@ -1,23 +1,25 @@
#! /usr/bin/env python
#!/usr/bin/env python
"""Generate XML file from YAML input"""
import xml.etree.ElementTree as ET
from pprint import pprint
import argparse
import os
import yaml

zm_num_entries = 1024

#% %
def make_node(parent: ET.Element, myid: str, thedict: dict, addr2: int,
def make_node(parent: ET.Element, myid: str, thedict: dict, addr2: int, bit: int,
parent_id: str) -> ET.Element:
"""create the node to be inserted into the xml tree"""
# pylint: disable=too-many-branches
# I disable this check because as far as I can tell it's wrong
#I disable this check because as far as I can tell it's wrong
thenode = ET.SubElement(parent, 'node')
myid = myid.replace(' ', '_')
thenode.set('id', myid)
#address is half of the sensor address since these are 32 bit addresses
theaddr = int(addr2/2)
remain = addr2 % 2
remain = bit
thenode.set('address', str(hex(theaddr)))
#this appears to be on all the nodes
thenode.set("permission", "r")
Expand Down Expand Up @@ -90,11 +92,12 @@ def calc_size(thedict: dict) -> int:
#and a pretty print method
class reg:
"""create an object with a name, and a start end end register"""
def __init__(self, name, sta, end, sz):
def __init__(self, name, sta, end, sz, width):
self.name = name
self.start = sta
self.end = end
self.size = sz
self.width = width

def __str__(self):
return "name: " + self.name + " start: " + str(self.start) + \
Expand All @@ -112,12 +115,11 @@ def overlaps(self, other):

def overloads(self):
"""check if the object overloads the register space"""
if self.start + self.size >= 255:
if self.start + self.size >= zm_num_entries - 1:
return True
return False


# custom file type for yaml file, to be used with argparse
#custom file type for yaml file, to be used with argparse
def yaml_file(filename):
"""custom file type for yaml file, to be used with argparse"""
if not filename.endswith('.yml'):
Expand All @@ -128,7 +130,7 @@ def yaml_file(filename):
parser.add_argument('-v', '--verbose', action='store_true',
help='increase output verbosity')
parser.add_argument('-d', '--directory', type=str, help='output directory')
# this argument is required, one input file ending with yaml extension
#this argument is required, one input file ending with yaml extension
parser.add_argument('input_file', metavar='file', type=yaml_file,
help='input yaml file name')

Expand All @@ -153,39 +155,64 @@ def yaml_file(filename):
cm = ET.Element('node')
cm.set('id', 'CM')
cm.set('address', '0x00000000')

prev_addr = 0x0 #keep track of the most recent address that comes into a pair of bytes for 8-bit masking
prev_j = 0x0 #keep track of the order of postfixes in each name node
prev_bit = 0x0 #keep track of the even or odd order of bytes globally sent for masking
#% %
config = y['config']

for c in config: # loop over entries in configuration (sensor category)
i = 0 # counter over the number of sensors within a category
names = c['names']
start = c['start']
count = c['count']
for n in names: # loop over names of sensors within a category
if (n=="R0B" and start!=prev_start+prev_count+1): #clkmonr0a and clkmon are from the same function in zynqmontask
print("warning: the start address of clkmon should continue from clkr0a")
if 'postfixes' in c:
pp = node = ET.SubElement(cm, 'node')
pp.set('id', n)
start = c['start']
addr = int((start + i)/2)
pp.set('address', str(hex(addr)))
postfixes = c['postfixes']
j = 0
for p in postfixes:
addr = int((start + i)/2)
bit = i%2
if p == 'RESERVED':
i += 1
j += 1
continue
if args.verbose:
print("adding postfix", p, "to node", n)
node = make_node(pp, p, c, j, n)
if (bit == 1 and j == 0): #the previous name node has odd bytes so this postfix node uses the previous postfix address but masks off the lower byte
pp = node = ET.SubElement(cm, 'node')
pp.set('id', n)
pp.set('address', str(hex(prev_addr)))
node = make_node(pp, p, c, j, bit, n)
elif (bit == 0 and j == 0): #starting a new postfix node in a new name node
pp = node = ET.SubElement(cm, 'node')
pp.set('id', n)
pp.set('address', str(hex(addr)))
node = make_node(pp, p, c, j, bit, n)
else: # any non-first byte in a name node
if (prev_bit == 0): #the upper byte of the previous postfix node
node = make_node(pp, p, c, j, bit, n)
else : #the low byte with an increasing postfix node by one
node = make_node(pp, p, c, j+1, bit, n)
if (prev_bit == bit and prev_addr == addr and prev_addr != 0) :
print("warning : please check if masks overlapped at node ", n, " addr ", hex(prev_addr))
prev_addr = addr
prev_j = j
prev_bit = bit
i += 1
j += 1
else:
start = c['start']
make_node(cm, n, c, start+i, "")
make_node(cm, n, c, start+i, (start+i)%2, "")
if (prev_bit == (start+i)%2 and prev_addr == int((start+i)/2) and prev_addr != 0) :
print("warning : please check if masks overlapped at node ", n, " addr ", hex(prev_addr))
prev_addr = int((start + i)/2)
prev_bit = (start+i)%2
i += 1
prev_start = start
prev_count = count

tree = ET.ElementTree(cm)
ET.indent(tree, space='\t')
# create output file name based on input file, replacing 'yml' with 'xml'
#create output file name based on input file, replacing 'yml' with 'xml'
out_name = os.path.basename(args.input_file)[:-len('.yml')] + '.xml'
out_name = args.directory + '/' + out_name
if args.verbose:
Expand All @@ -209,7 +236,20 @@ def yaml_file(filename):
postfixes = ' '
size = calc_size(c)
thislength = len(postfixes) * len(names)*size
entries.append(reg(c['name'], start, start + thislength - 1, thislength))
width = 99
if c['type'] == 'int8':
width = 8
elif c['type'] == 'int16':
width = 16
elif c['type'] == 'fp16':
width = 16
elif c['type'] == 'char':
width = 16
elif c['type'] == 'uint32_t':
width = 32
elif c['type'] == 'uint16_t':
width = 16
entries.append(reg(c['name'], start, start + thislength - 1, thislength, width))
if args.verbose:
for e in entries:
print(e)
Expand Down

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