Preprocessor: Whtespace after `define was not kept.

[puffsun]

Describe the bug

Sorry if I'm choose a wrong issue type. The issue is related to SystemVerilog preprocessor. After preprocessing include directives, a whitespace should be kept after each define. Please help.

Short summary.

The whitespace should be kept after `define.

To Reproduce

The included code is like:
included.v:

`ifndef SOMETHING
`define SOMETHING
  ...
`endif

top.v:

```systemverilog
`include "included.v"

module dummy_module(input clk);
endmodule

After preprocessing top.v, the output would be:

`defineSOMETHING
...

module dummy_module(input clk);
endmodule

Include any options used.

Actual behavior:
The file can be preprocessed without error, but the result is not fully expected.

Did it reject valid code? or crash?
No

Expected behavior

The whitespace after `define should be kept, or it will be invalid code.

A clear and concise description of what you expected to happen. Citations to the
SystemVerilog-2017 Standard (LRM)
would help.

[hzeller]

This is probably related to #1376 just before the GSoC time was running out.
Tom, we should get Karim on board :)