SVA Multi-clocked property leads to parser error

[ajeethakv]

Describe the bug
Parser seems to reject multi-clocked SVA. Other parsers/tools work fine on this code.

Short summary.

To Reproduce
verible-verilog-syntax file.sv

// Test case (preferably reduced) that illustrates the problem.
module reardyack;
  timeunit 1ns;  timeprecision 100ps;    
  bit clk, req, rdy, ack;
  XXXap_reqrdyack_bad: assert property(@ (posedge clk) (req ##1 rdy) |->  @ (posedge clk) @ (posedge clk) ack);

  endmodule

Actual behavior:

v.sv:4:75: syntax error at token "@"

Did it reject valid code? or crash?
Rejects valid code.