Add ifdef formatting

[wsnyder]

Please consider adding to verible-format-verilog support for ifdef/ifndef/elsif formatting, similar to Verilog-mode verilog-indent-level-directives Presumably an option is needed to set indent level, defaulting to 0 for old behavior. E.g. should result in this output when set to 1:

`define A
`ifdef A
 `define HAVE_A
 `ifdef C
  `define HAVE_AC
 `elsif A
  `define HAVE_AA
  `ifdef C
   `define HAVE_AC
  `elsif B
   `define HAVE_AB
  `else
   `define HAVE_AX
  `endif
 `else
  `define HAVE_AnA
 `endif
 `elsif B
  `define HAVE_AnB
  `endif
`endif