Need a flag to quiet syntax errors and do formatting for those files as well!

[SunilSegu]

Hi,

I was integrating this verible tool in our flow for formatting especially for indentation! When I tried executing verible-verilog-format --inplace . I can see files which has syntax issues are not getting formatted and tool is firing syntax issues.

Can we have a flag to disable syntax issues and do regular formatting for them! I have tried to disable syntax error prints from verilog-format.cc by adding a quiet flag. By this tool stopped firing syntax issues but its not formatting it! Can you please check as its benifical for all sv coders whose code is not required for synthesies!

Example:
File which has this kind of format has syntax issues!

interface my_interface()

logic signal_1;
`ifdef DEFINED
logic signal_2;
`endif

endinterface

[rimanov2000]

I'm experiencing a similar issue. When Verible encounters a syntax error (such as unrecognized macros from open-source packages), it stops formatting the rest of the code. This seems counterintuitive, as formatting should be independent of compilation/parsing success.

I tried disabling syntax checking with the --nopush_diagnostic_notifications argument. While this removes the red underlines for macro errors, it also removes the yellow formatting indicators (such as trailing whitespace warnings or overly long lines). Unfortunately, this argument appears to disable formatting entirely, not just error reporting.

[hzeller]

Right now, this is unfortunately the way the formatter is implemented: it takes a fully parsed syntax tree and then does formatting on that. What it should do instead is to work on the token stream which allows for a much more forgiving way of dealing with the formatting.

So, it is a known issues, and is on the TODO list to switch to token formatting, but there are also many other projects competing for my attention :) So for now, only files that can be parsed syntax-error free can be formatted.

[SunilSegu]

Hi,

Thanks for the comment. Is there any ETA scheduled for this?

[hzeller]

No schedule, sorry. I am busy with other things currently and can't plan for that. Pull requests are accepted, but it will require some detailed knowledge, so will not be done in a day.

There are knowledgeable folks that could implement things on a contract basis if you have a budget...

[SunilSegu]

Hi,

As you told its in TO DO list I asked for an ETA. I am not asking this to resolve in one day. Just asking if it's planned to done in next releases of verible.

And FYI I was able to supress the syntax error prints by using a quiet Flag which is passed as argument to the verible-verilog-format command. And I was able to indent those syntax error prone lines based on a fallback formatter approach which does indentation based on the tokens. But the indentation is not upto the mark. If you can let me know by which release this can be implemented we will update our flows with this. Right now we incorporated present tool which I edited which works based on quiet flag.

Hope you got the point.

Regards,
Sunil.