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Use variable before declaration #372

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stephenry opened this issue Jul 23, 2020 · 2 comments
Closed

Use variable before declaration #372

stephenry opened this issue Jul 23, 2020 · 2 comments
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style-linter Verilog style-linter issues

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@stephenry
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stephenry commented Jul 23, 2020

In the example below, foo is assigned before it is declared and is therefore infered as the 'default net type' according to 6.10, even if the eventual type is not the default net type. SV2V picks this up and causes the generated result to be incorrect; generates a wire. Yosys subsequently raises a warning as the wire is assigned from the sequential block. Verible (linter) should flag instances such as this where the variable use preceeds the declaration.

always_comb foo = 'b1;
logic foo;
@fangism
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fangism commented Jul 23, 2020

Someone was working on this in #217
Duplicate of #217

@fangism
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fangism commented Jul 23, 2020

Welcome to join the conversation there and comment on the #244

@fangism fangism closed this as completed Jul 23, 2020
@fangism fangism added the style-linter Verilog style-linter issues label Jul 23, 2020
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Labels
style-linter Verilog style-linter issues
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