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2021-1_EmbeddedSystem

순차정렬 후 중앙값 구하는 embedded hardware

  • verilog module & testbench
  • Xlinx CORE Generator: dual port SRAM
  • ModelSim : Simulation
  • Xlinx ISE: RTL Synthesis by XST

blockDiagram

HLSM

Simulation

1psim2 4psim2

Timing Summary

1p_timingSummary 4pchange_timingSummary

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