Skip to content

Commit 5e0476b

Browse files
committed
add tests for SMV LTLSPEC
1 parent 4c18952 commit 5e0476b

12 files changed

+162
-0
lines changed
Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
CORE broken-smt-backend
2+
smv_ltlspec_F3.smv
3+
--bound 10
4+
^\[.*\] F x = 0: REFUTED$
5+
^Counterexample with 4 states:$
6+
^x@0 = 1$
7+
^x@1 = 2$
8+
^x@2 = 3$
9+
^x@3 = 3$
10+
^EXIT=10$
11+
^SIGNAL=0$
12+
--
13+
^warning: ignoring
Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
MODULE main
2+
3+
VAR x : 0..3;
4+
5+
ASSIGN
6+
init(x) := 1;
7+
8+
next(x) :=
9+
case
10+
x=3 : 3;
11+
TRUE: x+1;
12+
esac;
13+
14+
-- trace should be 1, 2, 3, 3, ...
15+
LTLSPEC F x = 0
Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
CORE broken-smt-backend
2+
smv_ltlspec_G3.smv
3+
--bound 10
4+
^\[.*\] G X x != 3: REFUTED$
5+
^Counterexample with 3 states:$
6+
^x@0 = 1$
7+
^x@1 = 2$
8+
^x@2 = 3$
9+
^EXIT=10$
10+
^SIGNAL=0$
11+
--
12+
^warning: ignoring
Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
MODULE main
2+
3+
VAR x : 0..3;
4+
5+
ASSIGN
6+
init(x) := 1;
7+
8+
next(x) :=
9+
case
10+
x=3 : 3;
11+
TRUE: x+1;
12+
esac;
13+
14+
-- trace should be 1, 2, 3
15+
LTLSPEC G X x!=3
Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
KNOWNBUG broken-smt-backend
2+
smv_ltlspec_R2.smv
3+
--bound 10
4+
^\[.*\] FALSE R x != 3: REFUTED$
5+
^Counterexample with 4 states:$
6+
^x@0 = 1$
7+
^x@1 = 2$
8+
^x@2 = 3$
9+
^EXIT=10$
10+
^SIGNAL=0$
11+
--
12+
^warning: ignoring
13+
--
14+
The trace has too many states.
Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
MODULE main
2+
3+
VAR x : 0..3;
4+
5+
ASSIGN
6+
init(x) := 1;
7+
8+
next(x) :=
9+
case
10+
x=3 : 3;
11+
TRUE: x+1;
12+
esac;
13+
14+
-- trace should be 1, 2, 3
15+
LTLSPEC FALSE R x != 3
Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
KNOWNBUG broken-smt-backend
2+
smv_ltlspec_R3.smv
3+
--bound 1
4+
^\[.*\] FALSE R x != 3: PROVED up to bound 1$
5+
^EXIT=0$
6+
^SIGNAL=0$
7+
--
8+
^warning: ignoring
9+
--
10+
The counterexample is wrong.
Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
MODULE main
2+
3+
VAR x : 0..3;
4+
5+
ASSIGN
6+
init(x) := 1;
7+
8+
next(x) :=
9+
case
10+
x=3 : 3;
11+
TRUE: x+1;
12+
esac;
13+
14+
-- trace should be 1, 2, 3
15+
-- hence no trace with k=1
16+
LTLSPEC FALSE R x != 3
Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
CORE broken-smt-backend
2+
smv_ltlspec_R4.smv
3+
--bound 10
4+
^\[.*\] FALSE R x != 0: PROVED up to bound 10$
5+
^EXIT=0$
6+
^SIGNAL=0$
7+
--
8+
^warning: ignoring
9+
--
Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
MODULE main
2+
3+
VAR x : 0..3;
4+
5+
ASSIGN
6+
init(x) := 1;
7+
8+
next(x) :=
9+
case
10+
x=3 : 3;
11+
TRUE: x+1;
12+
esac;
13+
14+
-- should pass
15+
LTLSPEC FALSE R x != 0
Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
KNOWNBUG broken-smt-backend
2+
smv_ltlspec_U2.smv
3+
--bound 10
4+
^\[.*\] TRUE U x = 0: REFUTED$
5+
^Counterexample with 4 states:$
6+
^x@0 = 1$
7+
^x@1 = 2$
8+
^x@2 = 3$
9+
^x@3 = 3$
10+
^EXIT=10$
11+
^SIGNAL=0$
12+
--
13+
^warning: ignoring
Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
MODULE main
2+
3+
VAR x : 0..3;
4+
5+
ASSIGN
6+
init(x) := 1;
7+
8+
next(x) :=
9+
case
10+
x=3 : 3;
11+
TRUE: x+1;
12+
esac;
13+
14+
-- trace should be 1, 2, 3, 3, ...
15+
LTLSPEC TRUE U x = 0

0 commit comments

Comments
 (0)