Merge pull request #772 from diffblue/indexed-part-select-is-verilog

Verilog: indexed part select is Verilog 2005
diffblue · Oct 17, 2024 · c12e5ff · c12e5ff
2 parents 5b3e023 + c193387
commit c12e5ff
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Showing 5 changed files with 6 additions and 6 deletions.
diff --git a/regression/verilog/part-select/indexed-part-select2.desc b/regression/verilog/part-select/indexed-part-select2.desc
@@ -1,5 +1,5 @@
 CORE
-indexed-part-select2.sv
+indexed-part-select2.v
 
 ^file .* line 4: expected constant expression, but got `main\.width'$
 ^EXIT=2$

diff --git a/...rilog/part-select/indexed-part-select2.sv → ...erilog/part-select/indexed-part-select2.v b/...rilog/part-select/indexed-part-select2.sv → ...erilog/part-select/indexed-part-select2.v
diff --git a/regression/verilog/part-select/indexed-part-select4.sv b/regression/verilog/part-select/indexed-part-select4.sv
@@ -1,8 +1,8 @@
 module main(input my_input);
 
-  bit [7:0] some_wire;
+  reg [7:0] some_wire;
 
-  always @my_input begin
+  always @my_input begin : my_block
     integer i;
     for(i=0; i<4; i++)
       // part select with index known at synthesis time

diff --git a/regression/verilog/part-select/indexed-part-select5.sv b/regression/verilog/part-select/indexed-part-select5.sv
@@ -1,6 +1,6 @@
 module main(input my_input);
 
-  bit [7:0] some_wire;
+  reg [7:0] some_wire;
 
   always @my_input begin
     some_wire[0 +: 2] = 'b01;

diff --git a/src/verilog/scanner.l b/src/verilog/scanner.l
@@ -231,6 +231,8 @@ void verilog_scanner_init()
 ">>>"           { return TOK_GREATERGREATERGREATER; }
 "<<"            { return TOK_LESSLESS; }
 "<<<"           { return TOK_LESSLESSLESS; }
+"+:"            { return TOK_PLUSCOLON; } // V2005
+"-:"            { return TOK_MINUSCOLON; } // V2005
 
                 /* Trinary operators */
 
@@ -244,8 +246,6 @@ void verilog_scanner_init()
 "++"            { SYSTEM_VERILOG_OPERATOR(TOK_PLUSPLUS, "++"); }
 "--"            { SYSTEM_VERILOG_OPERATOR(TOK_MINUSMINUS, "--"); }
 "+="            { SYSTEM_VERILOG_OPERATOR(TOK_PLUSEQUAL, "+="); }
-"+:"            { SYSTEM_VERILOG_OPERATOR(TOK_PLUSCOLON, "+:"); }
-"-:"            { SYSTEM_VERILOG_OPERATOR(TOK_MINUSCOLON, "-:"); }
 "-="            { SYSTEM_VERILOG_OPERATOR(TOK_MINUSEQUAL, "-="); }
 "*="            { SYSTEM_VERILOG_OPERATOR(TOK_ASTERICEQUAL, "*="); }
 "/="            { SYSTEM_VERILOG_OPERATOR(TOK_SLASHEQUAL, "+="); }