Ensure AllBitsSet for TYP_SIMD64 is correctly handled

dotnet · Mar 15, 2023 · 3f5f97b · 3f5f97b
1 parent b1c5dfe
commit 3f5f97b
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Showing 3 changed files with 9 additions and 2 deletions.
diff --git a/src/coreclr/jit/codegenxarch.cpp b/src/coreclr/jit/codegenxarch.cpp
@@ -489,7 +489,8 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre
             emitter* emit = GetEmitter();
             emitAttr attr = emitTypeSize(targetType);
 
-            if (vecCon->IsAllBitsSet())
+            // TODO-XARCH-AVX512: Remove the TYP_SIMD64 check once AllBitsSet for TYP_SIMD64 gets codegen support
+            if (vecCon->IsAllBitsSet() && !vecCon->TypeIs(TYP_SIMD64))
             {
                 if ((attr != EA_32BYTE) || compiler->compOpportunisticallyDependsOn(InstructionSet_AVX2))
                 {

diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp
@@ -4864,7 +4864,12 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
             {
                 level = 0;
 
+#if defined(TARGET_XARCH)
+                // TODO-XARCH-AVX512: Remove the TYP_SIMD64 check once AllBitsSet for TYP_SIMD64 gets codegen support
+                if ((tree->AsVecCon()->IsAllBitsSet() && !tree->TypeIs(TYP_SIMD64)) || tree->AsVecCon()->IsZero())
+#else
                 if (tree->AsVecCon()->IsAllBitsSet() || tree->AsVecCon()->IsZero())
+#endif // TARGET_*
                 {
                     // We generate `cmpeq* tgtReg, tgtReg`, which is 4-5 bytes, for AllBitsSet
                     // and generate `xorp* tgtReg, tgtReg`, which is 3-5 bytes, for Zero

diff --git a/src/coreclr/jit/lowerxarch.cpp b/src/coreclr/jit/lowerxarch.cpp
@@ -6817,8 +6817,9 @@ bool Lowering::IsContainableHWIntrinsicOp(GenTreeHWIntrinsic* parentNode, GenTre
             }
             else if (childNode->IsCnsVec())
             {
+                // TODO-XARCH-AVX512: Remove the TYP_SIMD64 check once AllBitsSet for TYP_SIMD64 gets codegen support
                 GenTreeVecCon* vecCon = childNode->AsVecCon();
-                canBeContained        = !vecCon->IsAllBitsSet() && !vecCon->IsZero();
+                canBeContained        = (!vecCon->IsAllBitsSet() || vecCon->TypeIs(TYP_SIMD64)) && !vecCon->IsZero();
             }
         }