Accelerate DAA ExternalDecimal.checkExternalDecimal api

Accelerate DAA ExternalDecimal.checkExternalDecimal api for verifying Zoned/External decimals using zNext instruction, Vector Test Zoned. This commit also includes changes required for generating Vector Test Zoned instruction. Signed-off-by: Shubham Verma <[email protected]>
eclipse-omr · Nov 5, 2024 · 7cbf69b · 7cbf69b
1 parent d6bbba7
commit 7cbf69b
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Showing 10 changed files with 74 additions and 11 deletions.
diff --git a/compiler/compile/ResolvedMethod.cpp b/compiler/compile/ResolvedMethod.cpp
@@ -180,10 +180,23 @@ bool TR_ResolvedMethod::isDAAPackedDecimalWrapperMethod()
 #endif
    }
 
+bool TR_ResolvedMethod::isDAAExternalDecimalWrapperMethod()
+   {
+#ifdef J9_PROJECT_SPECIFIC
+   if ( // DAA External Decimal check method
+      getRecognizedMethod() == TR::com_ibm_dataaccess_ExternalDecimal_checkExternalDecimal
+      )
+      {
+      return true;
+      }
+#endif
+   return false;
+   }
+
 bool TR_ResolvedMethod::isDAAWrapperMethod()
    {
 #ifdef J9_PROJECT_SPECIFIC
-   return isDAAMarshallingWrapperMethod() || isDAAPackedDecimalWrapperMethod();
+   return isDAAMarshallingWrapperMethod() || isDAAPackedDecimalWrapperMethod() || isDAAExternalDecimalWrapperMethod();
 #else
    return false;
 #endif
@@ -282,10 +295,23 @@ bool TR_ResolvedMethod::isDAAPackedDecimalIntrinsicMethod()
 #endif
    }
 
+bool TR_ResolvedMethod::isDAAExternalDecimalIntrinsicMethod()
+   {
+#ifdef J9_PROJECT_SPECIFIC
+   if (// DAA External Decimal check method
+      getRecognizedMethod() == TR::com_ibm_dataaccess_ExternalDecimal_checkExternalDecimal_
+      )
+      {
+      return true;
+      }
+#endif
+   return false;
+   }
+
 bool TR_ResolvedMethod::isDAAIntrinsicMethod()
    {
 #ifdef J9_PROJECT_SPECIFIC
-   return isDAAMarshallingIntrinsicMethod() || isDAAPackedDecimalIntrinsicMethod();
+   return isDAAMarshallingIntrinsicMethod() || isDAAPackedDecimalIntrinsicMethod() || isDAAExternalDecimalIntrinsicMethod();
 #else
    return false;
 #endif

diff --git a/compiler/compile/ResolvedMethod.hpp b/compiler/compile/ResolvedMethod.hpp
@@ -179,10 +179,12 @@ class TR_ResolvedMethod
    bool isDAAWrapperMethod();
    bool isDAAMarshallingWrapperMethod();
    bool isDAAPackedDecimalWrapperMethod();
+   bool isDAAExternalDecimalWrapperMethod();
 
    bool isDAAIntrinsicMethod();
    bool isDAAMarshallingIntrinsicMethod();
    bool isDAAPackedDecimalIntrinsicMethod();
+   bool isDAAExternalDecimalIntrinsicMethod();
 
    virtual void setMethodHandleLocation(uintptr_t *location);
    virtual uintptr_t *getMethodHandleLocation();

diff --git a/compiler/optimizer/ValuePropagationTable.hpp b/compiler/optimizer/ValuePropagationTable.hpp
@@ -918,6 +918,7 @@ TR::Node * constrainLongBitCount(OMR::ValuePropagation *vp, TR::Node *node);
 #define pdModifyPrecisionVPHandler constrainChildren
 #define countDigitsVPHandler constrainChildren
 #define BCDCHKVPHandler constrainBCDCHK
+#define zdchkVPHandler constrainChildren
 #endif
 
 const ValuePropagationPointerTable constraintHandlers;

diff --git a/compiler/z/codegen/ControlFlowEvaluator.cpp b/compiler/z/codegen/ControlFlowEvaluator.cpp
@@ -2316,6 +2316,12 @@ void OMR::Z::TreeEvaluator::createDAACondDeps(TR::Node * node, TR::RegisterDepen
          TR::TreeEvaluator::addToRegDep(daaDeps, daaInstr->getRegisterOperand(2), false);
          break;
          }
+      case TR::Instruction::IsVRIl: // VTZ
+         {
+         TR::TreeEvaluator::addToRegDep(daaDeps, daaInstr->getRegisterOperand(1), false);
+         TR::TreeEvaluator::addToRegDep(daaDeps, daaInstr->getRegisterOperand(2), false);
+         break;
+         }
       case TR::Instruction::IsVRRg: // VTP
          {
          TR::TreeEvaluator::addToRegDep(daaDeps, daaInstr->getRegisterOperand(1), false);

diff --git a/compiler/z/codegen/InstOpCode.cpp b/compiler/z/codegen/InstOpCode.cpp
@@ -130,6 +130,7 @@ OMR::Z::InstOpCode::copyBinaryToBufferWithoutClear(uint8_t *cursor, TR::InstOpCo
         case VRIg_FORMAT:
         case VRIh_FORMAT:
         case VRIi_FORMAT:
+        case VRIl_FORMAT:
         case VRRa_FORMAT:
         case VRRb_FORMAT:
         case VRRc_FORMAT:

diff --git a/compiler/z/codegen/S390Debug.cpp b/compiler/z/codegen/S390Debug.cpp
@@ -324,6 +324,7 @@ TR_Debug::printz(TR::FILE *pOutFile, TR::Instruction * instr)
       case TR::Instruction::IsVRIg:
       case TR::Instruction::IsVRIh:
       case TR::Instruction::IsVRIi:
+      case TR::Instruction::IsVRIl:
             print(pOutFile, (TR::S390VRIInstruction *) instr);
          break;
       case TR::Instruction::IsVRRa:
@@ -2757,7 +2758,7 @@ TR_Debug::print(TR::FILE *pOutFile, TR::S390VRIInstruction * instr)
          break;
       case TR::Instruction::IsVRIl:
          trfprintf(pOutFile, ",0x%x",
-               maskHalf(static_cast<TR::S390VRIkInstruction*>(instr)->getImmediateField5()));
+               maskHalf(static_cast<TR::S390VRIlInstruction*>(instr)->getImmediateField3()));
          break;
       default:
          TR_ASSERT(false, "Unknown VRI type");

diff --git a/compiler/z/codegen/S390GenerateInstructions.cpp b/compiler/z/codegen/S390GenerateInstructions.cpp
@@ -1786,6 +1786,27 @@ generateVRIkInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR:
    return new (INSN_HEAP) TR::S390VRIkInstruction(cg, op, n, targetReg, sourceReg2, sourceReg3, sourceReg4, constantImm5);
    }
 
+TR::Instruction *
+generateVRIlInstruction(
+                      TR::CodeGenerator        * cg,
+                      TR::InstOpCode::Mnemonic   op,
+                      TR::Node                 * n,
+                      TR::Register             * sourceReg1,
+                      TR::Register             * sourceReg2,
+                      uint16_t                   constantImm3)  /* 16 bits  */
+   {
+   TR::Instruction* instr =  new (INSN_HEAP) TR::S390VRIlInstruction(cg, op, n, sourceReg1, sourceReg2, constantImm3);
+
+#ifdef J9_PROJECT_SPECIFIC
+   if (op == TR::InstOpCode::VTZ)
+      {
+      generateS390DAAExceptionRestoreSnippet(cg, n, instr, op, false);
+      }
+#endif
+
+   return instr;
+   }
+
 /****** VRR ******/
 TR::Instruction *
 generateVRRaInstruction(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic op, TR::Node * n, TR::Register * targetReg, TR::Register * sourceReg2,

diff --git a/compiler/z/codegen/S390GenerateInstructions.hpp b/compiler/z/codegen/S390GenerateInstructions.hpp
@@ -1069,6 +1069,14 @@ TR::Instruction * generateVRIkInstruction(
                       TR::Register           * sourceReg4,
                       uint8_t                 constantImm5); /* 8 bits  */
 
+TR::Instruction * generateVRIlInstruction(
+                      TR::CodeGenerator    * cg,
+                      TR::InstOpCode::Mnemonic   op,
+                      TR::Node               * n,
+                      TR::Register           * sourceReg1,
+                      TR::Register           * sourceReg2,
+                      uint16_t                constantImm3);   /* 16 bits  */
+
 /****** VRR ******/
 TR::Instruction * generateVRRaInstruction(
                       TR::CodeGenerator     * cg         ,

diff --git a/compiler/z/codegen/S390Instruction.cpp b/compiler/z/codegen/S390Instruction.cpp
@@ -3815,7 +3815,7 @@ TR::S390VRIlInstruction::generateBinaryEncoding()
    uint8_t* cursor = preGenerateBinaryEncoding();
 
    // The Immediate field
-   *(reinterpret_cast<uint32_t*>(cursor + 2)) |= static_cast<uint32_t>(getImmediateField3()) << 4;
+   *(reinterpret_cast<uint32_t*>(cursor + 2)) |= static_cast<uint32_t>(getImmediateField3()) << 12;
 
    // Operands
    // First and second register operands for VRI-l map to second and third register fields

diff --git a/compiler/z/codegen/S390Instruction.hpp b/compiler/z/codegen/S390Instruction.hpp
@@ -5271,15 +5271,12 @@ class S390VRIlInstruction : public S390VRIInstruction
                           TR::CodeGenerator      * cg               = NULL,
                           TR::InstOpCode::Mnemonic          op      = TR::InstOpCode::bad,
                           TR::Node               * n                = NULL,
-                          TR::Register           * targetReg        = NULL,
-                          TR::Register           * sourceReg        = NULL,
+                          TR::Register           * sourceReg1        = NULL,
+                          TR::Register           * sourceReg2        = NULL,
                           uint16_t                 constantImm3     = 0)    /* 16 bits */
-   : S390VRIInstruction(cg, op, n, targetReg, constantImm3, 0, 0, 0, 0)
+   : S390VRIInstruction(cg, op, n, sourceReg1, constantImm3, 0, 0, 0, 0)
       {
-      if (getOpCode().setsOperand2())
-         useTargetRegister(sourceReg);
-      else
-         useSourceRegister(sourceReg);
+      useSourceRegister(sourceReg2);
       }
 
    uint16_t getImmediateField3() { return getImmediateField16(); }