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Add zNext support #7525

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merged 8 commits into from
Jan 30, 2025
Merged

Add zNext support #7525

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03cfa30
Add support for zNext processor
Spencer-Comin Sep 20, 2023
1704d4a
Add opcode property for emulatable instructions
Spencer-Comin Oct 31, 2023
03840ab
Use load indexed address instructions for aladd and aiadd
Spencer-Comin Oct 30, 2023
64c42b0
Add use of count leading and trailing zeros instruction for zNext
dchopra001 Sep 6, 2023
9dde624
Accelerate Integer and Long expand and compress methods
Spencer-Comin Nov 8, 2023
6b31f74
Move canEmulate from Instruction to InstOpCode
VermaSh Dec 8, 2023
230a527
Accelerate DAA ExternalDecimal.checkExternalDecimal api
VermaSh Dec 1, 2023
2657050
Add codegen query for supporting LXA instructions
r30shah Jan 20, 2025
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6 changes: 5 additions & 1 deletion compiler/optimizer/RedundantAsyncCheckRemoval.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -424,7 +424,11 @@ bool TR_RedundantAsyncCheckRemoval::callDoesAnImplicitAsyncCheck(TR::Node *callN
(symbol->getRecognizedMethod()==TR::java_lang_Integer_rotateLeft) ||
(symbol->getRecognizedMethod()==TR::java_lang_Long_rotateLeft) ||
(symbol->getRecognizedMethod()==TR::java_lang_Integer_rotateRight) ||
(symbol->getRecognizedMethod()==TR::java_lang_Long_rotateRight)
(symbol->getRecognizedMethod()==TR::java_lang_Long_rotateRight) ||
(symbol->getRecognizedMethod()==TR::java_lang_Integer_compress) ||
(symbol->getRecognizedMethod()==TR::java_lang_Long_compress) ||
(symbol->getRecognizedMethod()==TR::java_lang_Integer_expand) ||
(symbol->getRecognizedMethod()==TR::java_lang_Long_expand)
)
return false;

Expand Down
1 change: 1 addition & 0 deletions compiler/optimizer/ValuePropagationTable.hpp
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Expand Up @@ -918,6 +918,7 @@ TR::Node * constrainLongBitCount(OMR::ValuePropagation *vp, TR::Node *node);
#define pdModifyPrecisionVPHandler constrainChildren
#define countDigitsVPHandler constrainChildren
#define BCDCHKVPHandler constrainBCDCHK
#define zdchkVPHandler constrainChildren
#endif

const ValuePropagationPointerTable constraintHandlers;
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6 changes: 6 additions & 0 deletions compiler/z/codegen/ControlFlowEvaluator.cpp
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Expand Up @@ -2343,6 +2343,12 @@ void OMR::Z::TreeEvaluator::createDAACondDeps(TR::Node * node, TR::RegisterDepen
TR::TreeEvaluator::addToRegDep(daaDeps, daaInstr->getRegisterOperand(2), false);
break;
}
case TR::Instruction::IsVRIl: // VTZ
{
TR::TreeEvaluator::addToRegDep(daaDeps, daaInstr->getRegisterOperand(1), false);
TR::TreeEvaluator::addToRegDep(daaDeps, daaInstr->getRegisterOperand(2), false);
break;
}
case TR::Instruction::IsVRRg: // VTP
{
TR::TreeEvaluator::addToRegDep(daaDeps, daaInstr->getRegisterOperand(1), false);
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2 changes: 2 additions & 0 deletions compiler/z/codegen/InstOpCode.cpp
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Expand Up @@ -119,6 +119,7 @@ OMR::Z::InstOpCode::copyBinaryToBufferWithoutClear(uint8_t *cursor, TR::InstOpCo
case RXF_FORMAT:
case RXYa_FORMAT:
case RXYb_FORMAT:
case RXYc_FORMAT:
case SIY_FORMAT:
case VRIa_FORMAT:
case VRIb_FORMAT:
Expand All @@ -129,6 +130,7 @@ OMR::Z::InstOpCode::copyBinaryToBufferWithoutClear(uint8_t *cursor, TR::InstOpCo
case VRIg_FORMAT:
case VRIh_FORMAT:
case VRIi_FORMAT:
case VRIl_FORMAT:
case VRRa_FORMAT:
case VRRb_FORMAT:
case VRRc_FORMAT:
Expand Down
67 changes: 67 additions & 0 deletions compiler/z/codegen/OMRCodeGenerator.cpp
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Expand Up @@ -408,6 +408,64 @@ OMR::Z::CodeGenerator::lowerTreeIfNeeded(
}
}

static bool disableLXAUncommoning = feGetEnv("TR_disableLXAUncommoning") != NULL;

if (!disableLXAUncommoning &&
(node->getOpCodeValue() == TR::aiadd || node->getOpCodeValue() == TR::aladd) &&
!parent->getOpCode().isLoad() &&
self()->getUseLXAInstructions())
{
// To enable generating more LXAs, perform uncommoning on trees that look like this:
// axadd
// <address>
// sub/add
// mul/shl
// <index>
// <constant stride>
// <constant offset>

TR::Node *addChild = node->getSecondChild();
if (addChild->getOpCode().isAdd() || addChild->getOpCode().isSub())
{
TR::Node *offsetChild = addChild->getSecondChild();
TR::Node *mulChild = addChild->getFirstChild();
if (offsetChild->getOpCode().isLoadConst() &&
(mulChild->getOpCode().isMul() || mulChild->getOpCode().isLeftShift()))
{
TR::Node *indexChild = mulChild->getFirstChild();
TR::Node *strideChild = mulChild->getSecondChild();
if (strideChild->getOpCode().isLoadConst())
{
int64_t stride = strideChild->getConstValue();
if (mulChild->getOpCode().isLeftShift())
stride = 1 << stride;

int64_t offset = offsetChild->getConstValue();
if ((stride == 1 || stride == 2 || stride == 4 || stride == 8 || stride == 16) &&
offset % stride == 0 &&
self()->isDispInRange(offset / stride))
{
// tree has correct shape, perform uncommoning
if (addChild->getReferenceCount() > 1 &&
performTransformation(self()->comp(), "%sFound LXA shaped axadd tree [%p]; performing uncommoning on add child [%p]\n", OPT_DETAILS, node, addChild))
{
node->setChild(1, addChild->uncommon());
}
if (mulChild->getReferenceCount() > 1 &&
performTransformation(self()->comp(), "%sFound LXA shaped axadd tree [%p]; performing uncommoning on mul child [%p]\n", OPT_DETAILS, node, mulChild))
{
addChild->setChild(0, mulChild->uncommon());
}
if (indexChild->getOpCodeValue() == TR::i2l &&
performTransformation(self()->comp(), "%sFound LXA shaped axadd tree [%p]; removing i2l on index child [%p]\n", OPT_DETAILS, node, indexChild))
{
mulChild->setChild(0, indexChild->uncommon());
}
}
}
}
}
}
}

bool OMR::Z::CodeGenerator::supportsInliningOfIsInstance()
Expand Down Expand Up @@ -587,6 +645,15 @@ OMR::Z::CodeGenerator::initialize()
comp->setOption(TR_DisableVectorBCD);
}

static bool canEmulateLXA = TR::InstOpCode(TR::InstOpCode::LXAB).canEmulate() &&
TR::InstOpCode(TR::InstOpCode::LXAH).canEmulate() &&
TR::InstOpCode(TR::InstOpCode::LXAF).canEmulate() &&
TR::InstOpCode(TR::InstOpCode::LXAG).canEmulate() &&
TR::InstOpCode(TR::InstOpCode::LXAQ).canEmulate();
if (canEmulateLXA || comp->target().cpu.isAtLeast(OMR_PROCESSOR_S390_ZNEXT))
{
cg->setUseLXAInstructions(true);
}
// Be pessimistic until we can prove we don't exit after doing code-generation
cg->setExitPointsInMethod(true);

Expand Down
14 changes: 11 additions & 3 deletions compiler/z/codegen/OMRCodeGenerator.hpp
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Expand Up @@ -505,6 +505,9 @@ class OMR_EXTENSIBLE CodeGenerator : public OMR::CodeGenerator
bool getCondCodeShouldBePreserved() { return _cgFlags.testAny(S390CG_condCodeShouldBePreserved); }
void setCondCodeShouldBePreserved(bool b) { _cgFlags.set(S390CG_condCodeShouldBePreserved, b); }

bool getUseLXAInstructions() { return _cgFlags.testAny(S390CG_useLXAInstructions); }
void setUseLXAInstructions(bool b) { _cgFlags.set(S390CG_useLXAInstructions, b); }

uint8_t getFCondMoveBranchOpCond() { return fCondMoveBranchOpCond; }
void setFCondMoveBranchOpCond(TR::InstOpCode::S390BranchCondition b) { fCondMoveBranchOpCond = (getMaskForBranchCondition(b)) & 0xF; }

Expand Down Expand Up @@ -722,8 +725,13 @@ class OMR_EXTENSIBLE CodeGenerator : public OMR::CodeGenerator

int32_t arrayTranslateAndTestMinimumNumberOfIterations() { return 4; }

/** Yank the scaling opp up a tree in lowerTrees */
bool yankIndexScalingOp() {return true;}
/**
* Yank the scaling op up a tree in lowerTrees
*/
bool yankIndexScalingOp()
{
return !getUseLXAInstructions();
}

bool excludeInvariantsFromGRAEnabled();

Expand Down Expand Up @@ -831,7 +839,7 @@ class OMR_EXTENSIBLE CodeGenerator : public OMR::CodeGenerator
S390CG_condCodeShouldBePreserved = 0x00004000,
S390CG_enableBranchPreload = 0x00008000,
S390CG_globalStaticBaseRegisterOn = 0x00010000,
// Available = 0x00020000,
S390CG_useLXAInstructions = 0x00020000,
S390CG_canExceptByTrap = 0x00040000,
S390CG_enableTLHPrefetching = 0x00080000,
S390CG_enableBranchPreloadForCalls = 0x00100000,
Expand Down
28 changes: 26 additions & 2 deletions compiler/z/codegen/OMRInstOpCode.enum
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Expand Up @@ -1161,7 +1161,7 @@
VLBRREP, // vector load byte reversed element and replicate
VLEBRF, // vector load byte reversed element (32)
VLEBRG, // vector load byte reversed element (64)
VLEBRH, // vector load byte reversed element (16)
VLEBRH, // vector load byte reversed element (16)
VLER, // vector load elements reversed
VLLEBRZ, // vector load byte reversed element and zero
VSTBR, // vector store byte reversed elements
Expand All @@ -1179,4 +1179,28 @@
VUPKZL, // VECTOR UNPACK ZONED LOW
VUPKZH, // VECTOR UNPACK ZONED HIGH

S390LastOp = VUPKZH,
/* zNext Instructions */
BDEPG, // BIT DEPOSIT
BEXTG, // BIT EXTRACT
CLZG, // COUNT LEADING ZEROS
CTZG, // COUNT TRAILING ZEROS
LLXAB, // LOAD LOGICAL INDEXED ADDRESS (8)
LLXAF, // LOAD LOGICAL INDEXED ADDRESS (32)
LLXAG, // LOAD LOGICAL INDEXED ADDRESS (64)
LLXAH, // LOAD LOGICAL INDEXED ADDRESS (16)
LLXAQ, // LOAD LOGICAL INDEXED ADDRESS (128)
LXAB, // LOAD INDEXED ADDRESS (8)
LXAF, // LOAD INDEXED ADDRESS (32)
LXAG, // LOAD INDEXED ADDRESS (64)
LXAH, // LOAD INDEXED ADDRESS (16)
LXAQ, // LOAD INDEXED ADDRESS (128)
VBLEND, // VECTOR BLEND
VEVAL, // VECTOR EVALUATE
VD, // VECTOR DIVIDE
VDL, // VECTOR DIVIDE LOGICAL
VGEM, // VECTOR GENERATE ELEMENT MASKS
VR, // VECTOR REMAINDER
VRL, // VECTOR REMAINDER LOGICAL
VTZ, // VECTOR TEST ZONED

S390LastOp = VTZ,
130 changes: 71 additions & 59 deletions compiler/z/codegen/OMRInstOpCode.hpp
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Expand Up @@ -282,7 +282,7 @@ namespace Z
#define RSa_FORMAT 36
#define RSb_FORMAT 37
#define RSI_FORMAT 38
#define RSLa_FORMAT 40
#define RSLa_FORMAT 40
#define RSLb_FORMAT 41
#define RSYa_FORMAT 43
#define RSYb_FORMAT 44
Expand All @@ -292,45 +292,48 @@ namespace Z
#define RXF_FORMAT 49
#define RXYa_FORMAT 51
#define RXYb_FORMAT 52
#define S_FORMAT 53
#define SI_FORMAT 54
#define SIL_FORMAT 55
#define SIY_FORMAT 56
#define SMI_FORMAT 57
#define SSa_FORMAT 60
#define SSb_FORMAT 61
#define SSc_FORMAT 62
#define SSd_FORMAT 63
#define SSe_FORMAT 64
#define SSf_FORMAT 65
#define SSE_FORMAT 66
#define SSF_FORMAT 67
#define VRIa_FORMAT 68
#define VRIb_FORMAT 69
#define VRIc_FORMAT 70
#define VRId_FORMAT 71
#define VRIe_FORMAT 72
#define VRIf_FORMAT 73
#define VRIg_FORMAT 74
#define VRIh_FORMAT 75
#define VRIi_FORMAT 76
#define VRRa_FORMAT 77
#define VRRb_FORMAT 78
#define VRRc_FORMAT 79
#define VRRd_FORMAT 80
#define VRRe_FORMAT 81
#define VRRf_FORMAT 82
#define VRRg_FORMAT 83
#define VRRh_FORMAT 84
#define VRRi_FORMAT 85
#define VRRk_FORMAT 86
#define VRSa_FORMAT 87
#define VRSb_FORMAT 88
#define VRSc_FORMAT 89
#define VRSd_FORMAT 90
#define VRV_FORMAT 91
#define VRX_FORMAT 92
#define VSI_FORMAT 93
#define RXYc_FORMAT 53
#define S_FORMAT 54
#define SI_FORMAT 55
#define SIL_FORMAT 56
#define SIY_FORMAT 57
#define SMI_FORMAT 60
#define SSa_FORMAT 61
#define SSb_FORMAT 62
#define SSc_FORMAT 63
#define SSd_FORMAT 64
#define SSe_FORMAT 65
#define SSf_FORMAT 66
#define SSE_FORMAT 67
#define SSF_FORMAT 68
#define VRIa_FORMAT 69
#define VRIb_FORMAT 70
#define VRIc_FORMAT 71
#define VRId_FORMAT 72
#define VRIe_FORMAT 73
#define VRIf_FORMAT 74
#define VRIg_FORMAT 75
#define VRIh_FORMAT 76
#define VRIi_FORMAT 77
#define VRIk_FORMAT 78
#define VRIl_FORMAT 79
#define VRRa_FORMAT 80
#define VRRb_FORMAT 81
#define VRRc_FORMAT 82
#define VRRd_FORMAT 83
#define VRRe_FORMAT 84
#define VRRf_FORMAT 85
#define VRRg_FORMAT 86
#define VRRh_FORMAT 87
#define VRRi_FORMAT 88
#define VRRk_FORMAT 89
#define VRSa_FORMAT 90
#define VRSb_FORMAT 91
#define VRSc_FORMAT 92
#define VRSd_FORMAT 93
#define VRV_FORMAT 94
#define VRX_FORMAT 95
#define VSI_FORMAT 96

/* Instruction Properties (One hot encoding) */
#define S390OpProp_None static_cast<uint64_t>(0x0000000000000000ull)
Expand Down Expand Up @@ -397,7 +400,7 @@ namespace Z
#define S390OpProp_ImplicitlySetsGPR3 static_cast<uint64_t>(0x1000000000000000ull)
#define S390OpProp_ImplicitlySetsGPR4 static_cast<uint64_t>(0x2000000000000000ull)
#define S390OpProp_ImplicitlySetsGPR5 static_cast<uint64_t>(0x4000000000000000ull)
// Available static_cast<uint64_t>(0x8000000000000000ull)
#define S390OpProp_IsEmulatable static_cast<uint64_t>(0x8000000000000000ull)

class InstOpCode: public OMR::InstOpCode
{
Expand All @@ -414,54 +417,54 @@ class InstOpCode: public OMR::InstOpCode
----------------------------------------- */
COND_NOPR, // Conditional Branch No operation (RR)
COND_NOP, // Conditional Branch No Operation (RX)
COND_VGNOP, // Virtual Guard No Operation
COND_BRO, // Relative Branch Branch Relative on Overflow
COND_VGNOP, // Virtual Guard No Operation
COND_BRO, // Relative Branch Branch Relative on Overflow
COND_BRH, // Relative Branch Branch Relative on High
COND_BRP, // Relative Branch Branch Relative on Plus
COND_BRP, // Relative Branch Branch Relative on Plus
COND_BRL, // Relative Branch Branch Relative on A Low
COND_BRM, // Relative Branch Branch Relative on Minus
COND_BRNE, // Relative Branch Branch Relative on A Not Equal B
COND_BRNZ, // Relative Branch Branch Relative on Not Zero
COND_BRE, // Relative Branch Branch Relative on A Equal B
COND_BRZ, // Relative Branch Branch Relative on Zero
COND_BRNH, // Relative Branch Branch Relative on A Not High
COND_BRE, // Relative Branch Branch Relative on A Equal B
COND_BRZ, // Relative Branch Branch Relative on Zero
COND_BRNH, // Relative Branch Branch Relative on A Not High
COND_BRNL, // Relative Branch Branch Relative on A Not Low
COND_BRNM, // Relative Branch Branch Relative on Not Minus
COND_BRNM, // Relative Branch Branch Relative on Not Minus
COND_BRNP, // Relative Branch Branch Relative on Not Plus
COND_BRNO, // Relative Branch Branch Relative on No Overflow
COND_BRNO, // Relative Branch Branch Relative on No Overflow
COND_B, // Conditional Branch Unconditional Branch (RX)
COND_BR, // Branch on Condition Unconditional Branch (RR)
COND_BRU, // Relative Branch Unconditional Branch Relative
COND_BRU, // Relative Branch Unconditional Branch Relative
COND_BRUL, // Relative Branch Unconditional Branch Relative
COND_BC, // Conditional Branch Branch on Condition (RX)
COND_BC, // Conditional Branch Branch on Condition (RX)
COND_BCR, // Conditional Branch Branch on Condition (RR)
COND_BE, // Conditional Branch Branch on A Equal B (RX)
COND_BER, // Conditional Branch Branch on A Equal B (RR)
COND_BER, // Conditional Branch Branch on A Equal B (RR)
COND_BH, // Conditional Branch Branch on A High (RX)
COND_BHR, // Conditional Branch Branch on A High (RR)
COND_BL, // Conditional Branch Branch on A Low (RX)
COND_BLR, // Conditional Branch Branch on A Low (RR)
COND_BLR, // Conditional Branch Branch on A Low (RR)
COND_BM, // Conditional Branch Branch on Minus (RX)
COND_BMR, // Conditional Branch Branch on Minus (RR)
COND_BNE, // Conditional Branch Branch on A Not Equal B (RX)
COND_BNER, // Conditional Branch Branch on A Not Equal B (RR)
COND_BNH, // Conditional Branch Branch on A Not High (RX)
COND_BNHR, // Conditional Branch Branch on A Not High (RR)
COND_BNHR, // Conditional Branch Branch on A Not High (RR)
COND_BNL, // Conditional Branch Branch on A Not Low (RX)
COND_BNLR, // Conditional Branch Branch on A Not Low (RR)
COND_BNLR, // Conditional Branch Branch on A Not Low (RR)
COND_BNM, // Conditional Branch Branch on Not Minus (RX)
COND_BNMR, // Conditional Branch Branch on Not Minus (RR)
COND_BNO, // Conditional Branch Branch on No Overflow (RX)
COND_BNOR, // Conditional Branch Branch on No Overflow (RR)
COND_BNP, // Conditional Branch Branch on Not Plus (RX)
COND_BNOR, // Conditional Branch Branch on No Overflow (RR)
COND_BNP, // Conditional Branch Branch on Not Plus (RX)
COND_BNPR, // Conditional Branch Branch on Not Plus (RR)
COND_BNZ, // Conditional Branch Branch on Not Zero (RX)
COND_BNZR, // Conditional Branch Branch on Not Zero (RR)
COND_BO, // Conditional Branch Branch on Overflow (RX)
COND_BO, // Conditional Branch Branch on Overflow (RX)
COND_BOR, // Conditional Branch Branch on Overflow (RR)
COND_BP, // Conditional Branch Branch on Plus (RX)
COND_BPR, // Conditional Branch Branch on Plus (RR)
COND_BRC, // Relative Branch Branch Relative on Condition
COND_BRC, // Relative Branch Branch Relative on Condition
COND_BZ, // Conditional Branch Branch on Zero (RX)
COND_BZR, // Conditional Branch Branch on Zero (RR)
COND_MASK0,
Expand Down Expand Up @@ -624,6 +627,15 @@ class InstOpCode: public OMR::InstOpCode
uint64_t hasExtendedMnemonic() {return metadata[_mnemonic].properties & S390OpProp_HasExtendedMnemonic;}
uint64_t isVectorStringOp() {return metadata[_mnemonic].properties & S390OpProp_VectorStringOp;}
uint64_t isVectorFPOp() {return metadata[_mnemonic].properties & S390OpProp_VectorFPOp;}
uint64_t isEmulatable() {return metadata[_mnemonic].properties & S390OpProp_IsEmulatable;}
bool canEmulate()
{
#ifdef EMULATE_ZNEXT
return isEmulatable();
#else
return false;
#endif
}

/* Static */
static void copyBinaryToBufferWithoutClear(uint8_t *cursor, Mnemonic i_opCode);
Expand Down
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