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FR: Extract FSM encodings

Feature RequestNew feature requestNew feature request

Vivado: Synthesis

Status: Open.

#23 In edaa-org/pyEDAA.OutputFilter;

· Paebbels opened on Jun 23, 2025

FR: Find unset signals

Feature RequestNew feature requestNew feature request

Vivado: Synthesis

Status: Open.

#22 In edaa-org/pyEDAA.OutputFilter;

· Paebbels opened on Jun 23, 2025

FR: Unused signals

Feature RequestNew feature requestNew feature request

Vivado: Synthesis

Status: Open.

#21 In edaa-org/pyEDAA.OutputFilter;

· Paebbels opened on Jun 23, 2025

FR: Collected loaded XDC files

Feature RequestNew feature requestNew feature request

Vivado: Implementation

Vivado: Synthesis

Status: Open.

#20 In edaa-org/pyEDAA.OutputFilter;

· Paebbels opened on Jun 23, 2025

FR: Extract design hierarchy by following synthesis messages

Feature RequestNew feature requestNew feature request

Vivado: Synthesis

Status: Open.

#19 In edaa-org/pyEDAA.OutputFilter;

· Paebbels opened on Jun 23, 2025

Vivado 2024.2 Synthesis Report Section "ROM, RAM, DSP, Shift Register and Retiming Reporting"

bugSomething isn't workingSomething isn't working

Vivado: Synthesis

Status: Open.

#18 In edaa-org/pyEDAA.OutputFilter;

· Jonas4242 opened on Jun 23, 2025