Add support for loading event variables in VCD/FST

[ripopov]

Verilog events are a special type of signal that represents discrete occurrences at specific time points,
unlike regular signals that maintain state between transitions.
All simulators I've tried to seem to dump each event as '1' value

#10
1'
#11
1'
#20
1'
..

Added Icarus Verilog output to example inputs.

Code generated by Claude, with minor human interventions.

[ripopov]

Did some research, found this:
https://gtkwave.github.io/gtkwave/man/gtkwaverc.5.html

vcd_preserve_glitches_real <value>
indicates that any repeat equal values for a real net spanning different time values in the VCD/FST file 
are not to be compressed into a single value change but should remain for this case. 
Default for vcd_preserve_glitches is disabled. The intended use is for when viewing analog 
interpolated data such that removing duplicate values would incorrectly deform the interpolation.

So there are other scenarios where duplicate filtering may be not desirable

[ekiwi]

That is fascinating. There was a reason why Surfer wanted duplicate values to be removed, but I forgot. I will review your PR next week. If you don't hear from me by next Friday, please tag me in a new comment on this issue and I will get to it.

[ripopov]

I've also tested this change manually by generating event rendering in Surfer:

One thing that requires attention is Compression::compress_with_options , since its public crate API, probably think how to make it extensible, for example #[non_exhaustive] struct? https://doc.rust-lang.org/reference/attributes/type_system.html

[ripopov]

There was a reason why Surfer wanted duplicate values to be removed, but I forgot.

Performance likely. Surfer already de-duplicates signals during its pre-render scan, I had to disable that mechanism for VcdEvent type in Surfer to render events.