Skip to content

Commit 7db83e7

Browse files
bugadanibugadani
committed
Remove redundant slow clock frequency metadata
1 parent 7a701f8 commit 7db83e7

File tree

17 files changed

+7
-112
lines changed

17 files changed

+7
-112
lines changed

‎esp-hal/src/ledc/timer.rs‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -225,6 +225,7 @@ pub struct Timer<'a, S: TimerSpeed> {
225225
duty: Option<config::Duty>,
226226
frequency: u32,
227227
configured: bool,
228+
#[cfg(soc_has_clock_node_ref_tick)]
228229
use_ref_tick: bool,
229230
clock_source: Option<S::ClockSourceType>,
230231
}
@@ -248,9 +249,11 @@ where
248249
let frequency: u32 = config.frequency.as_hz();
249250
self.frequency = frequency;
250251

252+
#[cfg_attr(not(soc_has_clock_node_ref_tick), expect(unused_mut))]
251253
let mut divisor = ((src_freq as u64) << 8) / frequency as u64 / precision as u64;
252254

253-
if divisor > LEDC_TIMER_DIV_NUM_MAX && cfg!(soc_ref_tick_hz_is_set) {
255+
#[cfg(soc_has_clock_node_ref_tick)]
256+
if divisor > LEDC_TIMER_DIV_NUM_MAX {
254257
// APB_CLK results in divisor which too high. Try using REF_TICK as clock
255258
// source.
256259
self.use_ref_tick = true;
@@ -299,6 +302,7 @@ impl<'a, S: TimerSpeed> Timer<'a, S> {
299302
duty: None,
300303
frequency: 0u32,
301304
configured: false,
305+
#[cfg(soc_has_clock_node_ref_tick)]
302306
use_ref_tick: false,
303307
clock_source: None,
304308
}
@@ -339,13 +343,13 @@ impl TimerHW<LowSpeed> for Timer<'_, LowSpeed> {
339343
/// Configure the HW for the timer
340344
fn configure_hw(&self, divisor: u32) {
341345
let duty = unwrap!(self.duty) as u8;
342-
let use_ref_tick = self.use_ref_tick;
343346

344347
self.ledc
345348
.timer(self.number as usize)
346349
.conf()
347350
.modify(|_, w| unsafe {
348-
w.tick_sel().bit(use_ref_tick);
351+
#[cfg(soc_has_clock_node_ref_tick)]
352+
w.tick_sel().bit(self.use_ref_tick);
349353
w.rst().clear_bit();
350354
w.pause().clear_bit();
351355
w.clk_div().bits(divisor);

‎esp-metadata-generated/src/_build_script_utils.rs‎

Lines changed: 0 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -279,12 +279,8 @@ impl Chip {
279279
"uart_uart0",
280280
"uart_uart1",
281281
"uart_uart2",
282-
"soc_ref_tick_hz=\"1000000\"",
283-
"soc_ref_tick_hz_is_set",
284282
"soc_rc_fast_clk_default=\"8500000\"",
285283
"soc_rc_fast_clk_default_is_set",
286-
"soc_rc_slow_clock=\"150000\"",
287-
"soc_rc_slow_clock_is_set",
288284
"soc_has_clock_node_xtal_clk",
289285
"soc_has_clock_node_pll_clk",
290286
"soc_has_clock_node_apll_clk",
@@ -478,12 +474,8 @@ impl Chip {
478474
"cargo:rustc-cfg=uart_uart0",
479475
"cargo:rustc-cfg=uart_uart1",
480476
"cargo:rustc-cfg=uart_uart2",
481-
"cargo:rustc-cfg=soc_ref_tick_hz=\"1000000\"",
482-
"cargo:rustc-cfg=soc_ref_tick_hz_is_set",
483477
"cargo:rustc-cfg=soc_rc_fast_clk_default=\"8500000\"",
484478
"cargo:rustc-cfg=soc_rc_fast_clk_default_is_set",
485-
"cargo:rustc-cfg=soc_rc_slow_clock=\"150000\"",
486-
"cargo:rustc-cfg=soc_rc_slow_clock_is_set",
487479
"cargo:rustc-cfg=soc_has_clock_node_xtal_clk",
488480
"cargo:rustc-cfg=soc_has_clock_node_pll_clk",
489481
"cargo:rustc-cfg=soc_has_clock_node_apll_clk",
@@ -804,8 +796,6 @@ impl Chip {
804796
"soc_cpu_has_csr_pc",
805797
"soc_rc_fast_clk_default=\"17500000\"",
806798
"soc_rc_fast_clk_default_is_set",
807-
"soc_rc_slow_clock=\"136000\"",
808-
"soc_rc_slow_clock_is_set",
809799
"soc_has_clock_node_xtal_clk",
810800
"soc_has_clock_node_pll_clk",
811801
"soc_has_clock_node_rc_fast_clk",
@@ -955,8 +945,6 @@ impl Chip {
955945
"cargo:rustc-cfg=soc_cpu_has_csr_pc",
956946
"cargo:rustc-cfg=soc_rc_fast_clk_default=\"17500000\"",
957947
"cargo:rustc-cfg=soc_rc_fast_clk_default_is_set",
958-
"cargo:rustc-cfg=soc_rc_slow_clock=\"136000\"",
959-
"cargo:rustc-cfg=soc_rc_slow_clock_is_set",
960948
"cargo:rustc-cfg=soc_has_clock_node_xtal_clk",
961949
"cargo:rustc-cfg=soc_has_clock_node_pll_clk",
962950
"cargo:rustc-cfg=soc_has_clock_node_rc_fast_clk",
@@ -1228,8 +1216,6 @@ impl Chip {
12281216
"soc_cpu_has_csr_pc",
12291217
"soc_rc_fast_clk_default=\"17500000\"",
12301218
"soc_rc_fast_clk_default_is_set",
1231-
"soc_rc_slow_clock=\"136000\"",
1232-
"soc_rc_slow_clock_is_set",
12331219
"soc_has_clock_node_xtal_clk",
12341220
"soc_has_clock_node_pll_clk",
12351221
"soc_has_clock_node_rc_fast_clk",
@@ -1420,8 +1406,6 @@ impl Chip {
14201406
"cargo:rustc-cfg=soc_cpu_has_csr_pc",
14211407
"cargo:rustc-cfg=soc_rc_fast_clk_default=\"17500000\"",
14221408
"cargo:rustc-cfg=soc_rc_fast_clk_default_is_set",
1423-
"cargo:rustc-cfg=soc_rc_slow_clock=\"136000\"",
1424-
"cargo:rustc-cfg=soc_rc_slow_clock_is_set",
14251409
"cargo:rustc-cfg=soc_has_clock_node_xtal_clk",
14261410
"cargo:rustc-cfg=soc_has_clock_node_pll_clk",
14271411
"cargo:rustc-cfg=soc_has_clock_node_rc_fast_clk",
@@ -1774,8 +1758,6 @@ impl Chip {
17741758
"soc_cpu_has_prv_mode",
17751759
"soc_rc_fast_clk_default=\"17500000\"",
17761760
"soc_rc_fast_clk_default_is_set",
1777-
"soc_rc_slow_clock=\"136000\"",
1778-
"soc_rc_slow_clock_is_set",
17791761
"soc_has_clock_node_xtal_clk",
17801762
"soc_has_clock_node_pll_clk",
17811763
"soc_has_clock_node_rc_fast_clk",
@@ -2028,8 +2010,6 @@ impl Chip {
20282010
"cargo:rustc-cfg=soc_cpu_has_prv_mode",
20292011
"cargo:rustc-cfg=soc_rc_fast_clk_default=\"17500000\"",
20302012
"cargo:rustc-cfg=soc_rc_fast_clk_default_is_set",
2031-
"cargo:rustc-cfg=soc_rc_slow_clock=\"136000\"",
2032-
"cargo:rustc-cfg=soc_rc_slow_clock_is_set",
20332013
"cargo:rustc-cfg=soc_has_clock_node_xtal_clk",
20342014
"cargo:rustc-cfg=soc_has_clock_node_pll_clk",
20352015
"cargo:rustc-cfg=soc_has_clock_node_rc_fast_clk",
@@ -2405,8 +2385,6 @@ impl Chip {
24052385
"soc_cpu_has_prv_mode",
24062386
"soc_rc_fast_clk_default=\"8500000\"",
24072387
"soc_rc_fast_clk_default_is_set",
2408-
"soc_rc_slow_clock=\"136000\"",
2409-
"soc_rc_slow_clock_is_set",
24102388
"soc_has_clock_node_xtal_clk",
24112389
"soc_has_clock_node_pll_f96m_clk",
24122390
"soc_has_clock_node_pll_f64m_clk",
@@ -2620,8 +2598,6 @@ impl Chip {
26202598
"cargo:rustc-cfg=soc_cpu_has_prv_mode",
26212599
"cargo:rustc-cfg=soc_rc_fast_clk_default=\"8500000\"",
26222600
"cargo:rustc-cfg=soc_rc_fast_clk_default_is_set",
2623-
"cargo:rustc-cfg=soc_rc_slow_clock=\"136000\"",
2624-
"cargo:rustc-cfg=soc_rc_slow_clock_is_set",
26252601
"cargo:rustc-cfg=soc_has_clock_node_xtal_clk",
26262602
"cargo:rustc-cfg=soc_has_clock_node_pll_f96m_clk",
26272603
"cargo:rustc-cfg=soc_has_clock_node_pll_f64m_clk",
@@ -2932,12 +2908,8 @@ impl Chip {
29322908
"timergroup_timg1",
29332909
"uart_uart0",
29342910
"uart_uart1",
2935-
"soc_ref_tick_hz=\"1000000\"",
2936-
"soc_ref_tick_hz_is_set",
29372911
"soc_rc_fast_clk_default=\"8500000\"",
29382912
"soc_rc_fast_clk_default_is_set",
2939-
"soc_rc_slow_clock=\"90000\"",
2940-
"soc_rc_slow_clock_is_set",
29412913
"soc_has_clock_node_xtal_clk",
29422914
"soc_has_clock_node_pll_clk",
29432915
"soc_has_clock_node_apll_clk",
@@ -3143,12 +3115,8 @@ impl Chip {
31433115
"cargo:rustc-cfg=timergroup_timg1",
31443116
"cargo:rustc-cfg=uart_uart0",
31453117
"cargo:rustc-cfg=uart_uart1",
3146-
"cargo:rustc-cfg=soc_ref_tick_hz=\"1000000\"",
3147-
"cargo:rustc-cfg=soc_ref_tick_hz_is_set",
31483118
"cargo:rustc-cfg=soc_rc_fast_clk_default=\"8500000\"",
31493119
"cargo:rustc-cfg=soc_rc_fast_clk_default_is_set",
3150-
"cargo:rustc-cfg=soc_rc_slow_clock=\"90000\"",
3151-
"cargo:rustc-cfg=soc_rc_slow_clock_is_set",
31523120
"cargo:rustc-cfg=soc_has_clock_node_xtal_clk",
31533121
"cargo:rustc-cfg=soc_has_clock_node_pll_clk",
31543122
"cargo:rustc-cfg=soc_has_clock_node_apll_clk",
@@ -3566,8 +3534,6 @@ impl Chip {
35663534
"uart_uart2",
35673535
"soc_rc_fast_clk_default=\"17500000\"",
35683536
"soc_rc_fast_clk_default_is_set",
3569-
"soc_rc_slow_clock=\"136000\"",
3570-
"soc_rc_slow_clock_is_set",
35713537
"soc_has_clock_node_xtal_clk",
35723538
"soc_has_clock_node_pll_clk",
35733539
"soc_has_clock_node_rc_fast_clk",
@@ -3803,8 +3769,6 @@ impl Chip {
38033769
"cargo:rustc-cfg=uart_uart2",
38043770
"cargo:rustc-cfg=soc_rc_fast_clk_default=\"17500000\"",
38053771
"cargo:rustc-cfg=soc_rc_fast_clk_default_is_set",
3806-
"cargo:rustc-cfg=soc_rc_slow_clock=\"136000\"",
3807-
"cargo:rustc-cfg=soc_rc_slow_clock_is_set",
38083772
"cargo:rustc-cfg=soc_has_clock_node_xtal_clk",
38093773
"cargo:rustc-cfg=soc_has_clock_node_pll_clk",
38103774
"cargo:rustc-cfg=soc_has_clock_node_rc_fast_clk",
@@ -4275,9 +4239,7 @@ pub fn emit_check_cfg_directives() {
42754239
println!("cargo:rustc-check-cfg=cfg(uart_uart0)");
42764240
println!("cargo:rustc-check-cfg=cfg(uart_uart1)");
42774241
println!("cargo:rustc-check-cfg=cfg(uart_uart2)");
4278-
println!("cargo:rustc-check-cfg=cfg(soc_ref_tick_hz_is_set)");
42794242
println!("cargo:rustc-check-cfg=cfg(soc_rc_fast_clk_default_is_set)");
4280-
println!("cargo:rustc-check-cfg=cfg(soc_rc_slow_clock_is_set)");
42814243
println!("cargo:rustc-check-cfg=cfg(soc_has_clock_node_xtal_clk)");
42824244
println!("cargo:rustc-check-cfg=cfg(soc_has_clock_node_pll_clk)");
42834245
println!("cargo:rustc-check-cfg=cfg(soc_has_clock_node_apll_clk)");
@@ -4531,13 +4493,9 @@ pub fn emit_check_cfg_directives() {
45314493
println!("cargo:rustc-check-cfg=cfg(soc_has_clock_node_apb_80m)");
45324494
println!("cargo:rustc-check-cfg=cfg(soc_has_clock_node_crypto_pwm_clk)");
45334495
println!("cargo:rustc-check-cfg=cfg(rmt_has_dma)");
4534-
println!("cargo:rustc-check-cfg=cfg(soc_ref_tick_hz, values(\"1000000\"))");
45354496
println!(
45364497
"cargo:rustc-check-cfg=cfg(soc_rc_fast_clk_default, values(\"8500000\",\"17500000\"))"
45374498
);
4538-
println!(
4539-
"cargo:rustc-check-cfg=cfg(soc_rc_slow_clock, values(\"150000\",\"136000\",\"90000\"))"
4540-
);
45414499
println!("cargo:rustc-check-cfg=cfg(gpio_gpio_function, values(\"2\",\"1\"))");
45424500
println!("cargo:rustc-check-cfg=cfg(gpio_constant_0_input, values(\"48\",\"31\",\"60\"))");
45434501
println!("cargo:rustc-check-cfg=cfg(gpio_constant_1_input, values(\"56\",\"30\"))");

‎esp-metadata-generated/src/_generated_esp32.rs‎

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -42,24 +42,12 @@ macro_rules! property {
4242
("soc.cpu_has_prv_mode") => {
4343
false
4444
};
45-
("soc.ref_tick_hz") => {
46-
1000000
47-
};
48-
("soc.ref_tick_hz", str) => {
49-
stringify!(1000000)
50-
};
5145
("soc.rc_fast_clk_default") => {
5246
8500000
5347
};
5448
("soc.rc_fast_clk_default", str) => {
5549
stringify!(8500000)
5650
};
57-
("soc.rc_slow_clock") => {
58-
150000
59-
};
60-
("soc.rc_slow_clock", str) => {
61-
stringify!(150000)
62-
};
6351
("aes.dma") => {
6452
false
6553
};

‎esp-metadata-generated/src/_generated_esp32c2.rs‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -48,12 +48,6 @@ macro_rules! property {
4848
("soc.rc_fast_clk_default", str) => {
4949
stringify!(17500000)
5050
};
51-
("soc.rc_slow_clock") => {
52-
136000
53-
};
54-
("soc.rc_slow_clock", str) => {
55-
stringify!(136000)
56-
};
5751
("assist_debug.has_sp_monitor") => {
5852
true
5953
};

‎esp-metadata-generated/src/_generated_esp32c3.rs‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -48,12 +48,6 @@ macro_rules! property {
4848
("soc.rc_fast_clk_default", str) => {
4949
stringify!(17500000)
5050
};
51-
("soc.rc_slow_clock") => {
52-
136000
53-
};
54-
("soc.rc_slow_clock", str) => {
55-
stringify!(136000)
56-
};
5751
("aes.dma") => {
5852
true
5953
};

‎esp-metadata-generated/src/_generated_esp32c6.rs‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -48,12 +48,6 @@ macro_rules! property {
4848
("soc.rc_fast_clk_default", str) => {
4949
stringify!(17500000)
5050
};
51-
("soc.rc_slow_clock") => {
52-
136000
53-
};
54-
("soc.rc_slow_clock", str) => {
55-
stringify!(136000)
56-
};
5751
("aes.dma") => {
5852
true
5953
};

‎esp-metadata-generated/src/_generated_esp32h2.rs‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -48,12 +48,6 @@ macro_rules! property {
4848
("soc.rc_fast_clk_default", str) => {
4949
stringify!(8500000)
5050
};
51-
("soc.rc_slow_clock") => {
52-
136000
53-
};
54-
("soc.rc_slow_clock", str) => {
55-
stringify!(136000)
56-
};
5751
("aes.dma") => {
5852
true
5953
};

‎esp-metadata-generated/src/_generated_esp32s2.rs‎

Lines changed: 0 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -42,24 +42,12 @@ macro_rules! property {
4242
("soc.cpu_has_prv_mode") => {
4343
false
4444
};
45-
("soc.ref_tick_hz") => {
46-
1000000
47-
};
48-
("soc.ref_tick_hz", str) => {
49-
stringify!(1000000)
50-
};
5145
("soc.rc_fast_clk_default") => {
5246
8500000
5347
};
5448
("soc.rc_fast_clk_default", str) => {
5549
stringify!(8500000)
5650
};
57-
("soc.rc_slow_clock") => {
58-
90000
59-
};
60-
("soc.rc_slow_clock", str) => {
61-
stringify!(90000)
62-
};
6351
("aes.dma") => {
6452
true
6553
};

‎esp-metadata-generated/src/_generated_esp32s3.rs‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -48,12 +48,6 @@ macro_rules! property {
4848
("soc.rc_fast_clk_default", str) => {
4949
stringify!(17500000)
5050
};
51-
("soc.rc_slow_clock") => {
52-
136000
53-
};
54-
("soc.rc_slow_clock", str) => {
55-
stringify!(136000)
56-
};
5751
("aes.dma") => {
5852
true
5953
};

‎esp-metadata/devices/esp32.toml‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -99,9 +99,7 @@ symbols = [
9999
]
100100

101101
[device.soc]
102-
ref_tick_hz = 1_000_000
103102
rc_fast_clk_default = 8_500_000
104-
rc_slow_clock = 150_000
105103

106104
memory_map = { ranges = [
107105
{ name = "dram", start = 0x3FFA_E000, end = 0x4000_0000 },

0 commit comments

Comments
 (0)