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Merged
copybara-service merged 3 commits into from
Apr 14, 2025
Merged

Support Sparse Inference for RVV #8081

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60d5e0b
Add RVV f32 SPMM kernel
yhng3010 Jan 9, 2025
f7e7eba
Add RVV f32-conv-hwc2chw-3x3s2p1c3 kernel
yhng3010 Feb 26, 2025
7de15ab
Add RVV f32-dwconv2d-chw kernel
yhng3010 Feb 26, 2025
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28 changes: 28 additions & 0 deletions bench/f32-conv-hwc2chw.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,7 @@
#include "src/xnnpack/buffer.h"
#include "src/xnnpack/common.h"
#include "src/xnnpack/conv.h"
#include "src/xnnpack/hardware-config.h"
#include "src/xnnpack/microfnptr.h"
#include "src/xnnpack/microparams-init.h"
#include "src/xnnpack/pack.h"
Expand Down Expand Up @@ -155,6 +156,33 @@ static void f32_conv_hwc2chw_3x3s2p1c3x4__wasmsimd_2x2(benchmark::State& state,
BENCHMARK_DCONV(f32_conv_hwc2chw_3x3s2p1c3x4__wasmsimd_2x2);
#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD

#if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV
static void f32_conv_hwc2chw_3x3s2p1c3x2v__rvv_1x1(benchmark::State& state,
const char* net) {
f32_conv_hwc2chw(state, xnn_f32_conv_hwc2chw_ukernel_3x3s2p1c3x2v__rvv_1x1,
xnn_init_f32_minmax_scalar_params,
2 * xnn_init_hardware_config()->vlenb / sizeof(float) /* output channel tile */);
}

static void f32_conv_hwc2chw_3x3s2p1c3x2v__rvv_2x1(benchmark::State& state,
const char* net) {
f32_conv_hwc2chw(state, xnn_f32_conv_hwc2chw_ukernel_3x3s2p1c3x2v__rvv_2x1,
xnn_init_f32_minmax_scalar_params,
2 * xnn_init_hardware_config()->vlenb / sizeof(float) /* output channel tile */);
}

static void f32_conv_hwc2chw_3x3s2p1c3x2v__rvv_2x2(benchmark::State& state,
const char* net) {
f32_conv_hwc2chw(state, xnn_f32_conv_hwc2chw_ukernel_3x3s2p1c3x2v__rvv_2x2,
xnn_init_f32_minmax_scalar_params,
2 * xnn_init_hardware_config()->vlenb / sizeof(float) /* output channel tile */);
}

BENCHMARK_DCONV(f32_conv_hwc2chw_3x3s2p1c3x2v__rvv_1x1);
BENCHMARK_DCONV(f32_conv_hwc2chw_3x3s2p1c3x2v__rvv_2x1);
BENCHMARK_DCONV(f32_conv_hwc2chw_3x3s2p1c3x2v__rvv_2x2);
#endif // XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV

static void f32_conv_hwc2chw_3x3s2p1c3x4__scalar_1x1(benchmark::State& state,
const char* net) {
f32_conv_hwc2chw(state, xnn_f32_conv_hwc2chw_ukernel_3x3s2p1c3x4__scalar_1x1,
Expand Down
150 changes: 150 additions & 0 deletions bench/f32-dwconv2d-chw.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -2837,6 +2837,156 @@ BENCHMARK_DWCONV(dwconv2d_chw_5x5s2p2__wasmsimd_x86_splat_2x4_acc3)
BENCHMARK_DWCONV(dwconv2d_chw_5x5s2p2__wasmsimd_x86_splat_3x4_acc2)
#endif // XNN_ARCH_WASMSIMD || XNN_ARCH_WASMRELAXEDSIMD

#if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV
static void dwconv2d_chw_3x3p1__rvv_5x1v(benchmark::State& state,
const char* net) {
f32_dwconv2d_chw(state,
xnn_f32_dwconv2d_chw_ukernel_3x3p1__rvv_5x1v,
xnn_init_f32_minmax_scalar_params,
/*kernel_height=*/3, /*kernel_width=*/3, /*padding_width=*/1,
/*stride=*/1);
}
static void dwconv2d_chw_3x3p1__rvv_6x1v(benchmark::State& state,
const char* net) {
f32_dwconv2d_chw(state,
xnn_f32_dwconv2d_chw_ukernel_3x3p1__rvv_6x1v,
xnn_init_f32_minmax_scalar_params,
/*kernel_height=*/3, /*kernel_width=*/3, /*padding_width=*/1,
/*stride=*/1);
}
static void dwconv2d_chw_3x3p1__rvv_7x1v(benchmark::State& state,
const char* net) {
f32_dwconv2d_chw(state,
xnn_f32_dwconv2d_chw_ukernel_3x3p1__rvv_7x1v,
xnn_init_f32_minmax_scalar_params,
/*kernel_height=*/3, /*kernel_width=*/3, /*padding_width=*/1,
/*stride=*/1);
}
static void dwconv2d_chw_3x3p1__rvv_8x1v(benchmark::State& state,
const char* net) {
f32_dwconv2d_chw(state,
xnn_f32_dwconv2d_chw_ukernel_3x3p1__rvv_8x1v,
xnn_init_f32_minmax_scalar_params,
/*kernel_height=*/3, /*kernel_width=*/3, /*padding_width=*/1,
/*stride=*/1);
}
static void dwconv2d_chw_3x3p1__rvv_1x2v(benchmark::State& state,
const char* net) {
f32_dwconv2d_chw(state,
xnn_f32_dwconv2d_chw_ukernel_3x3p1__rvv_1x2v,
xnn_init_f32_minmax_scalar_params,
/*kernel_height=*/3, /*kernel_width=*/3, /*padding_width=*/1,
/*stride=*/1);
}
static void dwconv2d_chw_3x3p1__rvv_2x2v(benchmark::State& state,
const char* net) {
f32_dwconv2d_chw(state,
xnn_f32_dwconv2d_chw_ukernel_3x3p1__rvv_2x2v,
xnn_init_f32_minmax_scalar_params,
/*kernel_height=*/3, /*kernel_width=*/3, /*padding_width=*/1,
/*stride=*/1);
}
static void dwconv2d_chw_3x3p1__rvv_3x2v(benchmark::State& state,
const char* net) {
f32_dwconv2d_chw(state,
xnn_f32_dwconv2d_chw_ukernel_3x3p1__rvv_3x2v,
xnn_init_f32_minmax_scalar_params,
/*kernel_height=*/3, /*kernel_width=*/3, /*padding_width=*/1,
/*stride=*/1);
}
static void dwconv2d_chw_3x3p1__rvv_4x2v(benchmark::State& state,
const char* net) {
f32_dwconv2d_chw(state,
xnn_f32_dwconv2d_chw_ukernel_3x3p1__rvv_4x2v,
xnn_init_f32_minmax_scalar_params,
/*kernel_height=*/3, /*kernel_width=*/3, /*padding_width=*/1,
/*stride=*/1);
}

static void dwconv2d_chw_3x3s2p1__rvv_5x1v(benchmark::State& state,
const char* net) {
f32_dwconv2d_chw(state,
xnn_f32_dwconv2d_chw_ukernel_3x3s2p1__rvv_5x1v,
xnn_init_f32_minmax_scalar_params,
/*kernel_height=*/3, /*kernel_width=*/3, /*padding_width=*/1,
/*stride=*/2);
}
static void dwconv2d_chw_3x3s2p1__rvv_6x1v(benchmark::State& state,
const char* net) {
f32_dwconv2d_chw(state,
xnn_f32_dwconv2d_chw_ukernel_3x3s2p1__rvv_6x1v,
xnn_init_f32_minmax_scalar_params,
/*kernel_height=*/3, /*kernel_width=*/3, /*padding_width=*/1,
/*stride=*/2);
}
static void dwconv2d_chw_3x3s2p1__rvv_7x1v(benchmark::State& state,
const char* net) {
f32_dwconv2d_chw(state,
xnn_f32_dwconv2d_chw_ukernel_3x3s2p1__rvv_7x1v,
xnn_init_f32_minmax_scalar_params,
/*kernel_height=*/3, /*kernel_width=*/3, /*padding_width=*/1,
/*stride=*/2);
}
static void dwconv2d_chw_3x3s2p1__rvv_8x1v(benchmark::State& state,
const char* net) {
f32_dwconv2d_chw(state,
xnn_f32_dwconv2d_chw_ukernel_3x3s2p1__rvv_8x1v,
xnn_init_f32_minmax_scalar_params,
/*kernel_height=*/3, /*kernel_width=*/3, /*padding_width=*/1,
/*stride=*/2);
}
static void dwconv2d_chw_3x3s2p1__rvv_1x2v(benchmark::State& state,
const char* net) {
f32_dwconv2d_chw(state,
xnn_f32_dwconv2d_chw_ukernel_3x3s2p1__rvv_1x2v,
xnn_init_f32_minmax_scalar_params,
/*kernel_height=*/3, /*kernel_width=*/3, /*padding_width=*/1,
/*stride=*/2);
}
static void dwconv2d_chw_3x3s2p1__rvv_2x2v(benchmark::State& state,
const char* net) {
f32_dwconv2d_chw(state,
xnn_f32_dwconv2d_chw_ukernel_3x3s2p1__rvv_2x2v,
xnn_init_f32_minmax_scalar_params,
/*kernel_height=*/3, /*kernel_width=*/3, /*padding_width=*/1,
/*stride=*/2);
}
static void dwconv2d_chw_3x3s2p1__rvv_3x2v(benchmark::State& state,
const char* net) {
f32_dwconv2d_chw(state,
xnn_f32_dwconv2d_chw_ukernel_3x3s2p1__rvv_3x2v,
xnn_init_f32_minmax_scalar_params,
/*kernel_height=*/3, /*kernel_width=*/3, /*padding_width=*/1,
/*stride=*/2);
}
static void dwconv2d_chw_3x3s2p1__rvv_4x2v(benchmark::State& state,
const char* net) {
f32_dwconv2d_chw(state,
xnn_f32_dwconv2d_chw_ukernel_3x3s2p1__rvv_4x2v,
xnn_init_f32_minmax_scalar_params,
/*kernel_height=*/3, /*kernel_width=*/3, /*padding_width=*/1,
/*stride=*/2);
}

BENCHMARK_DWCONV(dwconv2d_chw_3x3p1__rvv_5x1v)
BENCHMARK_DWCONV(dwconv2d_chw_3x3p1__rvv_6x1v)
BENCHMARK_DWCONV(dwconv2d_chw_3x3p1__rvv_7x1v)
BENCHMARK_DWCONV(dwconv2d_chw_3x3p1__rvv_8x1v)
BENCHMARK_DWCONV(dwconv2d_chw_3x3p1__rvv_1x2v)
BENCHMARK_DWCONV(dwconv2d_chw_3x3p1__rvv_2x2v)
BENCHMARK_DWCONV(dwconv2d_chw_3x3p1__rvv_3x2v)
BENCHMARK_DWCONV(dwconv2d_chw_3x3p1__rvv_4x2v)

BENCHMARK_DWCONV(dwconv2d_chw_3x3s2p1__rvv_5x1v)
BENCHMARK_DWCONV(dwconv2d_chw_3x3s2p1__rvv_6x1v)
BENCHMARK_DWCONV(dwconv2d_chw_3x3s2p1__rvv_7x1v)
BENCHMARK_DWCONV(dwconv2d_chw_3x3s2p1__rvv_8x1v)
BENCHMARK_DWCONV(dwconv2d_chw_3x3s2p1__rvv_1x2v)
BENCHMARK_DWCONV(dwconv2d_chw_3x3s2p1__rvv_2x2v)
BENCHMARK_DWCONV(dwconv2d_chw_3x3s2p1__rvv_3x2v)
BENCHMARK_DWCONV(dwconv2d_chw_3x3s2p1__rvv_4x2v)
#endif // XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV

static void dwconv2d_chw_3x3p1__scalar_1x1(benchmark::State& state,
const char* net) {
f32_dwconv2d_chw(state, xnn_f32_dwconv2d_chw_ukernel_3x3p1__scalar_1x1,
Expand Down
144 changes: 144 additions & 0 deletions bench/f32-spmm.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -232,6 +232,150 @@
#endif // XNN_ENABLE_HVX && XNN_ARCH_HEXAGON


#if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV
static void f32_spmm_minmax_ukernel_1vx1__rvv(benchmark::State& state, const char* net) {
f32_spmm(state, xnn_f32_spmm_minmax_ukernel_1vx1__rvv, 1 * xnn_init_hardware_config()->vlenb / sizeof(float), 1,
/*sparsity=*/0.8f, xnn_init_f32_minmax_scalar_params,
benchmark::utils::CheckRVV
);
}

BENCHMARK_SPMM(f32_spmm_minmax_ukernel_1vx1__rvv)
#endif // XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV


#if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV
static void f32_spmm_minmax_ukernel_1vx2__rvv(benchmark::State& state, const char* net) {
f32_spmm(state, xnn_f32_spmm_minmax_ukernel_1vx2__rvv, 1 * xnn_init_hardware_config()->vlenb / sizeof(float), 2,
/*sparsity=*/0.8f, xnn_init_f32_minmax_scalar_params,
benchmark::utils::CheckRVV
);
}

BENCHMARK_SPMM(f32_spmm_minmax_ukernel_1vx2__rvv)
#endif // XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV


#if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV
static void f32_spmm_minmax_ukernel_1vx4__rvv(benchmark::State& state, const char* net) {
f32_spmm(state, xnn_f32_spmm_minmax_ukernel_1vx4__rvv, 1 * xnn_init_hardware_config()->vlenb / sizeof(float), 4,
/*sparsity=*/0.8f, xnn_init_f32_minmax_scalar_params,
benchmark::utils::CheckRVV
);
}

BENCHMARK_SPMM(f32_spmm_minmax_ukernel_1vx4__rvv)
#endif // XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV


#if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV
static void f32_spmm_minmax_ukernel_2vx1__rvv(benchmark::State& state, const char* net) {
f32_spmm(state, xnn_f32_spmm_minmax_ukernel_2vx1__rvv, 2 * xnn_init_hardware_config()->vlenb / sizeof(float), 1,
/*sparsity=*/0.8f, xnn_init_f32_minmax_scalar_params,
benchmark::utils::CheckRVV
);
}

BENCHMARK_SPMM(f32_spmm_minmax_ukernel_2vx1__rvv)
#endif // XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV


#if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV
static void f32_spmm_minmax_ukernel_2vx2__rvv(benchmark::State& state, const char* net) {
f32_spmm(state, xnn_f32_spmm_minmax_ukernel_2vx2__rvv, 2 * xnn_init_hardware_config()->vlenb / sizeof(float), 2,
/*sparsity=*/0.8f, xnn_init_f32_minmax_scalar_params,
benchmark::utils::CheckRVV
);
}

BENCHMARK_SPMM(f32_spmm_minmax_ukernel_2vx2__rvv)
#endif // XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV


#if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV
static void f32_spmm_minmax_ukernel_2vx4__rvv(benchmark::State& state, const char* net) {
f32_spmm(state, xnn_f32_spmm_minmax_ukernel_2vx4__rvv, 2 * xnn_init_hardware_config()->vlenb / sizeof(float), 4,
/*sparsity=*/0.8f, xnn_init_f32_minmax_scalar_params,
benchmark::utils::CheckRVV
);
}

BENCHMARK_SPMM(f32_spmm_minmax_ukernel_2vx4__rvv)
#endif // XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV


#if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV
static void f32_spmm_minmax_ukernel_4vx1__rvv(benchmark::State& state, const char* net) {
f32_spmm(state, xnn_f32_spmm_minmax_ukernel_4vx1__rvv, 4 * xnn_init_hardware_config()->vlenb / sizeof(float), 1,
/*sparsity=*/0.8f, xnn_init_f32_minmax_scalar_params,
benchmark::utils::CheckRVV
);
}

BENCHMARK_SPMM(f32_spmm_minmax_ukernel_4vx1__rvv)
#endif // XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV


#if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV
static void f32_spmm_minmax_ukernel_4vx2__rvv(benchmark::State& state, const char* net) {
f32_spmm(state, xnn_f32_spmm_minmax_ukernel_4vx2__rvv, 4 * xnn_init_hardware_config()->vlenb / sizeof(float), 2,
/*sparsity=*/0.8f, xnn_init_f32_minmax_scalar_params,
benchmark::utils::CheckRVV
);
}

BENCHMARK_SPMM(f32_spmm_minmax_ukernel_4vx2__rvv)
#endif // XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV


#if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV
static void f32_spmm_minmax_ukernel_4vx4__rvv(benchmark::State& state, const char* net) {
f32_spmm(state, xnn_f32_spmm_minmax_ukernel_4vx4__rvv, 4 * xnn_init_hardware_config()->vlenb / sizeof(float), 4,
/*sparsity=*/0.8f, xnn_init_f32_minmax_scalar_params,
benchmark::utils::CheckRVV
);
}

BENCHMARK_SPMM(f32_spmm_minmax_ukernel_4vx4__rvv)
#endif // XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV


#if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV
static void f32_spmm_minmax_ukernel_8vx1__rvv(benchmark::State& state, const char* net) {
f32_spmm(state, xnn_f32_spmm_minmax_ukernel_8vx1__rvv, 8 * xnn_init_hardware_config()->vlenb / sizeof(float), 1,
/*sparsity=*/0.8f, xnn_init_f32_minmax_scalar_params,
benchmark::utils::CheckRVV
);
}

BENCHMARK_SPMM(f32_spmm_minmax_ukernel_8vx1__rvv)
#endif // XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV


#if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV
static void f32_spmm_minmax_ukernel_8vx2__rvv(benchmark::State& state, const char* net) {
f32_spmm(state, xnn_f32_spmm_minmax_ukernel_8vx2__rvv, 8 * xnn_init_hardware_config()->vlenb / sizeof(float), 2,
/*sparsity=*/0.8f, xnn_init_f32_minmax_scalar_params,
benchmark::utils::CheckRVV
);
}

BENCHMARK_SPMM(f32_spmm_minmax_ukernel_8vx2__rvv)
#endif // XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV


#if XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV
static void f32_spmm_minmax_ukernel_8vx4__rvv(benchmark::State& state, const char* net) {
f32_spmm(state, xnn_f32_spmm_minmax_ukernel_8vx4__rvv, 8 * xnn_init_hardware_config()->vlenb / sizeof(float), 4,
/*sparsity=*/0.8f, xnn_init_f32_minmax_scalar_params,
benchmark::utils::CheckRVV
);
}

BENCHMARK_SPMM(f32_spmm_minmax_ukernel_8vx4__rvv)
#endif // XNN_ENABLE_RISCV_VECTOR && XNN_ARCH_RISCV


#if XNN_ARCH_WASMRELAXEDSIMD
static void f32_spmm_minmax_ukernel_4x1__wasmrelaxedsimd_arm(benchmark::State& state, const char* net) {
f32_spmm(state, xnn_f32_spmm_minmax_ukernel_4x1__wasmrelaxedsimd_arm, 4, 1,
Expand Down
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