xls/modules/zstd: expose fifo verilog module

Signed-off-by: Pawel Czarnecki <[email protected]>

xls/modules/zstd/BUILD

@@ -33,6 +33,8 @@ package(
     licenses = ["notice"],
 )
 
+exports_files(["xls_fifo_wrapper.v"])
+
 xls_dslx_library(
     name = "buffer_dslx",
     srcs = [

xls/modules/zstd/memory/BUILD

@@ -403,6 +403,7 @@ verilog_library(
     name = "mem_reader_verilog_lib",
     srcs = [
         ":mem_reader.v",
+        "//xls/modules/zstd:xls_fifo_wrapper.v",
     ],
     tags = ["manual"],
 )
@@ -458,6 +459,7 @@ verilog_library(
     name = "mem_reader_adv_verilog_lib",
     srcs = [
         ":mem_reader_adv.v",
+        "//xls/modules/zstd:xls_fifo_wrapper.v",
     ],
     tags = ["manual"],
 )
@@ -496,6 +498,7 @@ py_test(
     data = [
         ":mem_reader_adv.v",
         ":mem_reader_wrapper.v",
+        "//xls/modules/zstd:xls_fifo_wrapper.v",
         "@com_icarus_iverilog//:iverilog",
         "@com_icarus_iverilog//:vvp",
     ],
@@ -741,6 +744,7 @@ verilog_library(
     name = "mem_writer_verilog_lib",
     srcs = [
         ":mem_writer.v",
+        "//xls/modules/zstd:xls_fifo_wrapper.v",
     ],
     tags = ["manual"],
 )
@@ -779,6 +783,7 @@ py_test(
     data = [
         ":mem_writer.v",
         ":mem_writer_wrapper.v",
+        "//xls/modules/zstd:xls_fifo_wrapper.v",
         "@com_icarus_iverilog//:iverilog",
         "@com_icarus_iverilog//:vvp",
     ],

xls/modules/zstd/memory/mem_reader_cocotb_test.py

@@ -264,6 +264,7 @@ async def mem_reader_aligned_transfer_shorter_than_bus4(dut):
 
   toplevel = "mem_reader_wrapper"
   verilog_sources = [
+    "xls/modules/zstd/xls_fifo_wrapper.v",
     "xls/modules/zstd/memory/mem_reader_adv.v",
     "xls/modules/zstd/memory/mem_reader_wrapper.v",
   ]

xls/modules/zstd/memory/mem_writer_cocotb_test.py

@@ -362,6 +362,7 @@ def generate_test_data_arbitrary(mem_size, test_cases):
 if __name__ == "__main__":
     toplevel = "mem_writer_wrapper"
     verilog_sources = [
+      "xls/modules/zstd/xls_fifo_wrapper.v",
       "xls/modules/zstd/memory/mem_writer.v",
       "xls/modules/zstd/memory/mem_writer_wrapper.v",
     ]

xls/modules/zstd/xls_fifo_wrapper.v

@@ -0,0 +1,53 @@
+// simple fifo implementation
+module xls_fifo_wrapper (
+clk, rst,
+push_ready, push_data, push_valid,
+pop_ready,  pop_data,  pop_valid);
+  parameter Width = 32,
+            Depth = 32,
+            EnableBypass = 0,
+            RegisterPushOutputs = 1,
+            RegisterPopOutputs = 1;
+  localparam AddrWidth = $clog2(Depth) + 1;
+  input  wire             clk;
+  input  wire             rst;
+  output wire             push_ready;
+  input  wire [Width-1:0] push_data;
+  input  wire             push_valid;
+  input  wire             pop_ready;
+  output wire [Width-1:0] pop_data;
+  output wire             pop_valid;
+
+  // Require depth be 1 and bypass disabled.
+  //initial begin
+  //  if (EnableBypass || Depth != 1 || !RegisterPushOutputs || RegisterPopOutputs) begin
+  //    // FIFO configuration not supported.
+  //    $fatal(1);
+  //  end
+  //end
+
+
+  reg [Width-1:0] mem;
+  reg full;
+
+  assign push_ready = !full;
+  assign pop_valid = full;
+  assign pop_data = mem;
+
+  always @(posedge clk) begin
+    if (rst == 1'b1) begin
+      full <= 1'b0;
+    end else begin
+      if (push_valid && push_ready) begin
+        mem <= push_data;
+        full <= 1'b1;
+      end else if (pop_valid && pop_ready) begin
+        mem <= mem;
+        full <= 1'b0;
+      end else begin
+        mem <= mem;
+        full <= full;
+      end
+    end
+  end
+endmodule