hdl: remove deprecated Past, Rose, Fell.

See amaranth-lang/amaranth@750cbbc
greatscottgadgets · Feb 5, 2024 · 119a3bf · 119a3bf
1 parent 76d2eed
commit 119a3bf
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Showing 4 changed files with 9 additions and 7 deletions.
diff --git a/luna/gateware/interface/gateware_phy/phy.py b/luna/gateware/interface/gateware_phy/phy.py
@@ -6,7 +6,6 @@
 import logging
 
 from amaranth         import Signal, Module, Cat, Elaboratable, ClockSignal
-from amaranth.hdl.ast import Rose, Past
 
 from .receiver      import RxPipeline
 from .transmitter   import TxPipeline

diff --git a/luna/gateware/interface/gateware_phy/receiver.py b/luna/gateware/interface/gateware_phy/receiver.py
@@ -34,7 +34,6 @@
 
 from amaranth          import Elaboratable, Module, Signal, Cat, Const, ClockSignal
 from amaranth.lib.fifo import AsyncFIFOBuffered
-from amaranth.hdl.ast  import Past
 from amaranth.hdl.xfrm import ResetInserter
 
 from ...utils.cdc import synchronize
@@ -622,10 +621,12 @@ def elaborate(self, platform):
         # 1bit->8bit (1byte) gearing
         #
         m.submodules.shifter = shifter = RxShifter(width=8)
+        past_o_pkt_active    = Signal.like(detect.o_pkt_active)
+        m.d.usb_io          += past_o_pkt_active.eq(detect.o_pkt_active)
         m.d.comb += [
             shifter.reset.eq(detect.o_pkt_end),
             shifter.i_data.eq(bitstuff.o_data),
-            shifter.i_valid.eq(~bitstuff.o_stall & Past(detect.o_pkt_active, domain="usb_io")),
+            shifter.i_valid.eq(~bitstuff.o_stall & past_o_pkt_active),
         ]
 
         #

diff --git a/luna/gateware/interface/ulpi.py b/luna/gateware/interface/ulpi.py
@@ -11,7 +11,6 @@
 
 from amaranth       import Signal, Module, Cat, Elaboratable, ClockSignal, \
                            Record, ResetSignal, Const
-from amaranth.hdl.ast import Rose, Fell, Past
 from amaranth.hdl.rec import Record, DIR_FANIN, DIR_FANOUT, DIR_NONE
 
 from ..utils.io     import delay
@@ -1296,7 +1295,9 @@ def elaborate(self, platform):
         # A transmission starts when DIR goes high with NXT, or when an RxEvent indicates
         # a switch from RxActive = 0 to RxActive = 1. A transmission stops when DIR drops low,
         # or when the RxEvent RxActive bit drops from 1 to 0, or an error occurs.A
-        dir_rising_edge = Rose(self.ulpi.dir.i, domain="usb")
+        past_dir        = Signal.like(self.ulpi.dir.i)
+        m.d.usb        += past_dir.eq(self.ulpi.dir.i)
+        dir_rising_edge = ~past_dir & self.ulpi.dir.i
         dir_based_start = dir_rising_edge & self.ulpi.nxt
 
 

diff --git a/luna/gateware/usb/usb2/endpoint.py b/luna/gateware/usb/usb2/endpoint.py
@@ -10,7 +10,6 @@
 import operator
 
 from amaranth         import Signal, Elaboratable, Module
-from amaranth.hdl.ast import Past
 
 from .packet          import DataCRCInterface, InterpacketTimerInterface, TokenDetectorInterface
 from .packet          import HandshakeExchangeInterface
@@ -265,7 +264,9 @@ def elaborate(self, platform):
 
         # We'll connect our PID toggle to whichever interface has a valid transmission going.
         for interface in self._interfaces:
-            with conditional(interface.tx.valid | Past(interface.tx.valid, domain="usb")):
+            past_valid = Signal.like(interface.tx.valid)
+            m.d.usb   += past_valid.eq(interface.tx.valid)
+            with conditional(interface.tx.valid | past_valid):
                 m.d.comb += shared.tx_pid_toggle.eq(interface.tx_pid_toggle)
 
             conditional = m.Elif