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Restore Fault #56

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36214da
Upgrade ngspice, fix build script
hpretl Jul 15, 2024
46f9804
Submodules now work, see https://github.com/IHP-GmbH/IHP-Open-PDK/iss…
hpretl Jul 16, 2024
50cbfaa
Remove short git hash from tool locations
hpretl Jul 20, 2024
b207440
Adding PULP tools bender, morty, and svase
hpretl Jul 20, 2024
cfdee86
Fix typo and shellcheck warnings
hpretl Jul 20, 2024
3264834
Need to uncomment this, otherwise fail
hpretl Jul 20, 2024
47e0ea8
Add Verible and SV2V
hpretl Jul 20, 2024
ccb731d
Update README.md
hpretl Jul 20, 2024
dd0421f
Fix build of svase
hpretl Jul 21, 2024
dcccbd4
A bit of cleanup
hpretl Jul 21, 2024
1761dd2
Add link (alias) for Xyce as xyce
hpretl Jul 21, 2024
537a53d
Update RELEASE_NOTES.md
hpretl Jul 21, 2024
368e415
Add debug info messages
hpretl Jul 21, 2024
4e8cc1f
Remove -j otherwise build fails
hpretl Jul 21, 2024
cdc9f18
Add Latex support for SVG backend in schemdraw
hpretl Jul 21, 2024
79a3942
Wrap yosys so that VHDL support in OpenLane2 works, see https://githu…
hpretl Jul 21, 2024
8c0ada1
Adding RISC-V toolchain back in for PULP platform
hpretl Jul 22, 2024
0cecae7
Fix Docker warning
hpretl Jul 22, 2024
36bcdcb
Enable RISC-V toolchain for 32b and 64b
hpretl Jul 22, 2024
5d66a3e
Remove rv32i, as we build now 64+32 variants
hpretl Jul 22, 2024
58e1471
Remove rv32i (missed one spot)
hpretl Jul 22, 2024
c708466
Build more parallel, since larger build machines
hpretl Jul 22, 2024
b1bb14d
Adapt to new build environment
hpretl Jul 22, 2024
1cfe1de
Revert "Build more parallel, since larger build machines"
hpretl Jul 23, 2024
64e7245
Adding surelog
hpretl Jul 23, 2024
2511d34
Removed netlistsvg (and therewith remove dependency on nodejs for now!).
MrHighVoltage Jul 23, 2024
3c919ff
Also remove netslistsvg entry in the README.
MrHighVoltage Jul 23, 2024
9228e5f
Update RELEASE_NOTES.md
hpretl Jul 23, 2024
c95c9d3
New build step needed in latest release
hpretl Jul 23, 2024
070061c
Bump tool version
hpretl Jul 23, 2024
0f160b2
Adding `pygmid` package
hpretl Jul 25, 2024
9343cc2
Set to parallel of 4
hpretl Jul 26, 2024
d1c7def
Making sure all pkgs build in /tmp
hpretl Jul 26, 2024
f630a76
Fix xyce build (after move to /tmp)
hpretl Jul 26, 2024
62e4f66
Update parallel to 6
hpretl Jul 26, 2024
5b9e5c1
Try to clean up Python pkgs
hpretl Jul 28, 2024
096861c
Remove `.git` from links
hpretl Jul 28, 2024
1127347
Adding `xcircuit`
hpretl Jul 28, 2024
28164bc
Initial attempt to restore fault
donn Jul 26, 2024
ecab9b7
Fix Docker warning
hpretl Jul 28, 2024
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16 changes: 14 additions & 2 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -84,8 +84,10 @@ Below is a list of the current tools already installed and ready to use (note th
* [covered](https://github.com/hpretl/verilog-covered) Verilog code coverage
* [cvc](https://github.com/d-m-bailey/cvc) circuit validity checker (ERC)
* [edalize](https://github.com/olofk/edalize) Python abstraction library for EDA tools
* [fault](https://github.com/AUCOHL/Fault) design-for-test (DFT) solution
* [fusesoc](https://github.com/olofk/fusesoc) package manager and build tools for SoC
* [gaw3-xschem](https://github.com/StefanSchippers/xschem-gaw.git) waveform plot tool for `xschem`
* [gaw3-xschem](https://github.com/StefanSchippers/xschem-gaw) waveform plot tool for `xschem`
* [gdsfactory](https://github.com/gdsfactory/gdsfactory) Python library for GDS generation
* [gdspy](https://github.com/heitzmann/gdspy) Python module for the creation and manipulation of GDS files
* [gds3d](https://github.com/trilomix/GDS3D) a 3D viewer for GDS files
Expand All @@ -95,11 +97,11 @@ Below is a list of the current tools already installed and ready to use (note th
* [sg13g2](https://github.com/IHP-GmbH/IHP-Open-PDK) IHP Microelectronics 130nm SiGe:C BiCMOS PDK (partial PDK, not fully supported yet; `xschem` and `ngspice` simulation works incl. PSP MOSFET model)
* [irsim](https://github.com/rtimothyedwards/irsim) switch-level digital simulator
* [iverilog](https://github.com/steveicarus/iverilog.git) Verilog simulator
* [iverilog](https://github.com/steveicarus/iverilog) Verilog simulator
* [hdl21](https://github.com/dan-fritchman/Hdl21) analog hardware description library
* [klayout](https://github.com/KLayout/klayout) layout viewer and editor for GDS and OASIS
* [libman](https://github.com/IHP-GmbH/LibMan) design library manager to manage cells and views
* [magic](https://github.com/rtimothyedwards/magic) layout editor with DRC and PEX
* [netlistsvg](https://github.com/nturley/netlistsvg) draws an SVG netlist from a `yosys` JSON netlist
* [netgen](https://github.com/rtimothyedwards/netgen) netlist comparison (LVS)
* [ngspice](http://ngspice.sourceforge.net) SPICE analog and mixed-signal simulator, with OSDI support
* [ngspyce](https://github.com/ignamv/ngspyce) Python bindings for `ngspice`
Expand All @@ -109,7 +111,11 @@ Below is a list of the current tools already installed and ready to use (note th
* [openram](https://github.com/VLSIDA/OpenRAM) OpenRAM Python library
* [openroad](https://github.com/The-OpenROAD-Project/OpenROAD.git) RTL2GDS engine used by `openlane2`
* [osic-multitool](https://github.com/iic-jku/osic-multitool.git) collection of useful scripts and documentation
* [openroad](https://github.com/The-OpenROAD-Project/OpenROAD) RTL2GDS engine used by `openlane2`
* [osic-multitool](https://github.com/iic-jku/osic-multitool) collection of useful scripts and documentation
* [padring](https://github.com/donn/padring) padring generation tool
* [pulp-tools](https://github.com/pulp-platform/pulp) PULP platform tools consisting of [bender](https://github.com/pulp-platform/bender), [morty](https://github.com/pulp-platform/morty), [svase](https://github.com/pulp-platform/svase), [verible](https://github.com/chipsalliance/verible), and [sv2v](https://github.com/zachjs/sv2v)
* [pygmid](https://github.com/dreoilin/pygmid) Python version of the gm/Id starter kit from Boris Murmann
* [pyopus](https://fides.fe.uni-lj.si/pyopus/index.html) simulation runner and optimization tool for analog circuits
* [pyrtl](https://github.com/UCSBarchlab/PyRTL) collection of classes for pythonic RTL design
* [pyspice](https://github.com/PySpice-org/PySpice) interface `ngspice` and `xyce` from Python
Expand All @@ -119,17 +125,23 @@ Below is a list of the current tools already installed and ready to use (note th
* [qucs-s](https://github.com/ra3xdh/qucs_s) simulation environment with RF emphasis
* [rggen](https://github.com/rggen/rggen) code generation tool for configuration and status registers
* [schemdraw](https://github.com/cdelker/schemdraw) Python package for drawing electrical schematics
* [spyci](https://github.com/gmagno/spyci) analyze/plot `ngspice`/`xyce` output data with Python
* [slang](https://github.com/MikePopoloski/slang) SystemVerilog parsing and translation (e.g. to Verilog)
* [spyci](https://github.com/gmagno/spyci) analyze/plot `ngspice`/`xyce` output data with Python
* [surelog](https://github.com/chipsalliance/Surelog) SystemVerilog parser, elaborator, and UHDM compiler
* [synlig](https://github.com/chipsalliance/synlig) SystemVerilog plugin for `yosys`
* [vlog2verilog](https://github.com/RTimothyEdwards/qflow.git) Verilog file conversion
* [vlog2verilog](https://github.com/RTimothyEdwards/qflow) Verilog file conversion
* [volare](https://github.com/efabless/volare) version manager (and builder) for open-source PDKs
* [risc-v toolchain](https://github.com/riscv/riscv-gnu-toolchain) GNU compiler toolchain for RISC-V cores
* [siliconcompiler](https://github.com/siliconcompiler/siliconcompiler) modular build system for hardware
* [sky130](https://github.com/google/skywater-pdk.git) SkyWater Technologies 130nm CMOS PDK
* [sky130](https://github.com/google/skywater-pdk) SkyWater Technologies 130nm CMOS PDK
* [verilator](https://github.com/verilator/verilator) fast Verilog simulator
* [vlsirtools](https://github.com/Vlsir/Vlsir) interchange formats for chip design.
* [xschem](https://github.com/StefanSchippers/xschem.git) schematic editor
* [xyce](https://github.com/Xyce/Xyce.git) fast parallel SPICE simulator (incl. `xdm` netlist conversion tool)
* [xcircuit](https://github.com/RTimothyEdwards/XCircuit) schematic drawing tool with SPICE export
* [xyce](https://github.com/Xyce/Xyce) fast parallel SPICE simulator (incl. `xdm` netlist conversion tool)
* [yosys](https://github.com/YosysHQ/yosys) Verilog synthesis tool (with GHDL plugin for VHDL synthesis), incl. `eqy` (equivalence checker), `sby` (formal verification), and `mcy` (mutation coverage)

The tool versions used for `OpenLane2` (and other tools) are documented in `tool_metadata.yml`. In addition to the EDA tools above, further valuable tools (like `git`) and editors (like `gvim`) are installed. If something useful is missing, please let us know!
Expand Down
11 changes: 11 additions & 0 deletions RELEASE_NOTES.md
Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,17 @@

This document summarizes the most important changes of the individual releases of the `IIC-OSIC-TOOLS` Docker container.

## 2024.08

* Add required tools for PULP-platform (morty, bender, svase, sv2v, verible).
* Add `surelog`.
* Add `pygmid`.
* Add `xcircuit`.
* Bump various tools versions.
* Fixed VHDL usage in OpenLane.
* Simplified tools paths by removing tool version.
* Remove `netlistsvg`, as it is requiring the large node.js package.

## 2024.07

* Bump various tool versions.
Expand Down
72 changes: 64 additions & 8 deletions _build/Dockerfile
Original file line number Diff line number Diff line change
Expand Up @@ -92,6 +92,19 @@ ARG CVC_RV_NAME="cvc_rv"
RUN --mount=type=bind,source=images/cvc_rv,target=/images/cvc_rv \
bash /images/cvc_rv/scripts/install.sh

#######################################################################
# Compile fault
#######################################################################
# FIXME build dependencies clean as stand-alone stages
FROM base AS fault
ARG FAULT_REPO_URL="https://github.com/AUCOHL/Fault.git"
ARG FAULT_REPO_COMMIT="0d42398b287fa8ed755f8f5bb518c14b65be4d52"
ARG FAULT_NAME="fault"
RUN --mount=type=bind,source=images/fault,target=/images/fault \
bash /images/fault/scripts/dependencies.sh
RUN --mount=type=bind,source=images/fault,target=/images/fault \
bash /images/fault/scripts/install.sh

#######################################################################
# Compile gaw3-xschem
#######################################################################
Expand All @@ -117,7 +130,7 @@ RUN --mount=type=bind,source=images/gds3d,target=/images/gds3d \
#######################################################################
FROM base AS ghdl
ARG GHDL_REPO_URL="https://github.com/ghdl/ghdl.git"
ARG GHDL_REPO_COMMIT="abe642a3c770ae2d3983cba5604b35c24fdcc6be"
ARG GHDL_REPO_COMMIT="5b5a300dacbac9658fefb4d2cada8ba1e67c331e"
ARG GHDL_NAME="ghdl"
RUN --mount=type=bind,source=images/ghdl,target=/images/ghdl \
bash /images/ghdl/scripts/install.sh
Expand Down Expand Up @@ -147,7 +160,7 @@ RUN --mount=type=bind,source=images/irsim,target=/images/irsim \
#######################################################################
FROM base AS iverilog
ARG IVERILOG_REPO_URL="https://github.com/steveicarus/iverilog.git"
ARG IVERILOG_REPO_COMMIT="cb6544fac3404cea6a5c204ac1cef93bfebcf919"
ARG IVERILOG_REPO_COMMIT="676b36e4554f119d0606ade79db2fba6834d3445"
ARG IVERILOG_NAME="iverilog"
RUN --mount=type=bind,source=images/iverilog,target=/images/iverilog \
bash /images/iverilog/scripts/install.sh
Expand Down Expand Up @@ -187,7 +200,7 @@ RUN --mount=type=bind,source=images/netgen,target=/images/netgen \
#######################################################################
FROM open_pdks AS ngspice
ARG NGSPICE_REPO_URL="https://github.com/danchitnis/ngspice-sf-mirror"
ARG NGSPICE_REPO_COMMIT="ngspice-42"
ARG NGSPICE_REPO_COMMIT="ngspice-43"
ARG NGSPICE_NAME="ngspice"
RUN --mount=type=bind,source=images/ngspice,target=/images/ngspice \
bash /images/ngspice/scripts/install.sh
Expand All @@ -207,7 +220,7 @@ RUN --mount=type=bind,source=images/ngspyce,target=/images/ngspyce \
#######################################################################
FROM base AS nvc
ARG NVC_REPO_URL="https://github.com/nickg/nvc"
ARG NVC_REPO_COMMIT="r1.12.2"
ARG NVC_REPO_COMMIT="r1.13.0"
ARG NVC_NAME="nvc"
RUN --mount=type=bind,source=images/nvc,target=/images/nvc \
bash /images/nvc/scripts/install.sh
Expand All @@ -232,6 +245,14 @@ ARG PADRING_NAME="padring"
RUN --mount=type=bind,source=images/padring,target=/images/padring \
bash /images/padring/scripts/install.sh

#######################################################################
# Compile pulp platform tools
#######################################################################
FROM base AS pulp-tools
ARG PULP_NAME="pulp"
RUN --mount=type=bind,source=images/pulp-tools,target=/images/pulp-tools \
bash /images/pulp-tools/scripts/install.sh

#######################################################################
# Compile pyopus
#######################################################################
Expand All @@ -242,6 +263,16 @@ ARG PYOPUS_NAME="pyopus"
RUN --mount=type=bind,source=images/pyopus,target=/images/pyopus \
bash /images/pyopus/scripts/install.sh

#######################################################################
# Compile surelog
#######################################################################
FROM base AS surelog
ARG SURELOG_REPO_URL="https://github.com/chipsalliance/Surelog"
ARG SURELOG_REPO_COMMIT="v1.83"
ARG SURELOG_NAME="surelog"
RUN --mount=type=bind,source=images/surelog,target=/images/surelog \
bash /images/surelog/scripts/install.sh

#######################################################################
# Compile qflow helper files
#######################################################################
Expand All @@ -257,17 +288,27 @@ RUN --mount=type=bind,source=images/qflow,target=/images/qflow \
#######################################################################
FROM base AS qucs-s
ARG QUCS_S_REPO_URL="https://github.com/ra3xdh/qucs_s"
ARG QUCS_S_REPO_COMMIT="24.2.1"
ARG QUCS_S_REPO_COMMIT="24.3.0"
ARG QUCS_S_NAME="qucs-s"
RUN --mount=type=bind,source=images/qucs-s,target=/images/qucs-s \
bash /images/qucs-s/scripts/install.sh

#######################################################################
# Compile riscv-gnu-toolchain
#######################################################################
FROM base AS riscv-gnu-toolchain
ARG RISCV_GNU_TOOLCHAIN_REPO_URL="https://github.com/riscv-collab/riscv-gnu-toolchain.git"
ARG RISCV_GNU_TOOLCHAIN_REPO_COMMIT="2024.04.12"
ARG RISCV_GNU_TOOLCHAIN_NAME="riscv-gnu-toolchain"
COPY images/riscv-gnu-toolchain/scripts/install.sh install.sh
RUN bash install.sh

#######################################################################
# Compile slang
#######################################################################
FROM base AS slang
ARG SLANG_REPO_URL="https://github.com/MikePopoloski/slang.git"
ARG SLANG_REPO_COMMIT="1b3255e68318a1a0ae6b9281c5c19f5e5b6cbc63"
ARG SLANG_REPO_COMMIT="928045a4da4e1239831b2d0cbd75f25b63ee07d5"
ARG SLANG_NAME="slang"
RUN --mount=type=bind,source=images/slang,target=/images/slang \
bash /images/slang/scripts/install.sh
Expand All @@ -282,12 +323,22 @@ ARG VERILATOR_NAME="verilator"
RUN --mount=type=bind,source=images/verilator,target=/images/verilator \
bash /images/verilator/scripts/install.sh

#######################################################################
# Compile xcircuit
#######################################################################
FROM base AS xcircuit
ARG XCIRCUIT_REPO_URL="https://github.com/RTimothyEdwards/XCircuit"
ARG XCIRCUIT_REPO_COMMIT="b6d0b096a6a4730a4255efb50191e03cfa9b5496"
ARG XCIRCUIT_NAME="xcircuit"
RUN --mount=type=bind,source=images/xcircuit,target=/images/xcircuit \
bash /images/xcircuit/scripts/install.sh

#######################################################################
# Compile xschem
#######################################################################
FROM base AS xschem
ARG XSCHEM_REPO_URL="https://github.com/StefanSchippers/xschem.git"
ARG XSCHEM_REPO_COMMIT="28bef9b06e657c69ec9f5e52fe9665d4d4c133ba"
ARG XSCHEM_REPO_COMMIT="8b5ed3f32ed77b67044b7097376e845be518cdc2"
ARG XSCHEM_NAME="xschem"
RUN --mount=type=bind,source=images/xschem,target=/images/xschem \
bash /images/xschem/scripts/install.sh
Expand Down Expand Up @@ -337,7 +388,7 @@ RUN --mount=type=bind,source=images/ghdl-yosys-plugin,target=/images/ghdl-yosys-

FROM base AS synlig-yosys-plugin
ARG SYNLIG_YOSYS_PLUGIN_REPO_URL="https://github.com/chipsalliance/synlig.git"
ARG SYNLIG_YOSYS_PLUGIN_REPO_COMMIT="320e2fdec5d37bf7acf2c1a5b6578997dd536f5f"
ARG SYNLIG_YOSYS_PLUGIN_REPO_COMMIT="3e3cdc33140edfd25cca5229555dcd6dc9d14468"
ARG SYNLIG_YOSYS_PLUGIN_NAME="synlig-yosys-plugin"
COPY --from=yosys ${TOOLS} ${TOOLS}
RUN --mount=type=bind,source=images/synlig-yosys-plugin,target=/images/synlig-yosys-plugin \
Expand Down Expand Up @@ -384,6 +435,7 @@ ENV OMPI_MCA_btl_vader_single_copy_mechanism=none
COPY --from=open_pdks ${PDK_ROOT}/ ${PDK_ROOT}/
COPY --from=covered ${TOOLS}/ ${TOOLS}/
COPY --from=cvc_rv ${TOOLS}/ ${TOOLS}/
COPY --from=fault ${TOOLS}/ ${TOOLS}/
COPY --from=gaw3-xschem ${TOOLS}/ ${TOOLS}/
COPY --from=gds3d ${TOOLS}/ ${TOOLS}/
COPY --from=gds3d ${PDK_ROOT}/ ${PDK_ROOT}/
Expand All @@ -402,12 +454,16 @@ COPY --from=openroad_app ${TOOLS}/ ${TOOLS}/
COPY --from=osic-multitool ${TOOLS}/ ${TOOLS}/
COPY --from=openvaf ${TOOLS}/ ${TOOLS}/
COPY --from=padring ${TOOLS}/ ${TOOLS}/
COPY --from=pulp-tools ${TOOLS}/ ${TOOLS}/
COPY --from=pyopus ${TOOLS}/ ${TOOLS}/
COPY --from=qflow ${TOOLS}/ ${TOOLS}/
COPY --from=qucs-s ${TOOLS}/ ${TOOLS}/
COPY --from=rftoolkit ${TOOLS}/ ${TOOLS}/
COPY --from=riscv-gnu-toolchain ${TOOLS}/ ${TOOLS}/
COPY --from=slang ${TOOLS}/ ${TOOLS}/
COPY --from=surelog ${TOOLS}/ ${TOOLS}/
COPY --from=verilator ${TOOLS}/ ${TOOLS}/
COPY --from=xcircuit ${TOOLS}/ ${TOOLS}/
COPY --from=xschem ${TOOLS}/ ${TOOLS}/
COPY --from=xyce ${TOOLS}/ ${TOOLS}/
COPY --from=xyce-xdm ${TOOLS}/ ${TOOLS}/
Expand Down
5 changes: 3 additions & 2 deletions _build/build-all.sh
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,7 @@ if [ -z ${DOCKER_TAGS+z} ]; then
fi

if [ -z ${DOCKER_PLATFORMS+z} ]; then
DOCKER_PLATFORMS="linux/amd64,linux/arm64/v8"
DOCKER_PLATFORMS="linux/amd64,linux/arm64"
fi

if [ -z ${DOCKER_LOAD+z} ]; then
Expand All @@ -51,7 +51,8 @@ fi

if [ -z ${BUILDER_STRS+z} ]; then
echo "Defining builder strs"
BUILDER_STRS="host=ssh://pretl@buildx86,host=unix:///var/run/docker.sock"
#BUILDER_STRS="host=ssh://pretl@buildx86,host=unix:///var/run/docker.sock"
BUILDER_STRS="host=ssh://pretl@buildx86,host=ssh://pretl@buildaarch"
fi

if [ -z ${BUILDER_NAME+z} ]; then
Expand Down
2 changes: 1 addition & 1 deletion _build/buildkitd.toml
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
[worker.oci]
# limit the number of parallel build steps that can run at the same time
max-parallelism = 2
max-parallelism = 6
gc = true
gckeepstorage = 60000
[[worker.oci.gcpolicy]]
Expand Down
21 changes: 0 additions & 21 deletions _build/images/base/scripts/00_base_install.sh
Original file line number Diff line number Diff line change
Expand Up @@ -127,8 +127,6 @@ apt -y install \
llvm-15-dev \
make \
ninja-build \
nodejs \
npm \
openmpi-bin \
openssl \
patch \
Expand Down Expand Up @@ -172,42 +170,25 @@ apt -y install \
python3-httpcore \
python3-httpx \
python3-immutabledict \
python3-ipykernel \
python3-ipython \
python3-ipywidgets \
python3-iso8601 \
python3-isodate \
python3-jedi \
python3-joblib \
python3-json5 \
python3-jsonschema \
python3-jupyter-client \
python3-jupyter-console \
python3-jupyter-core \
python3-jupyter-server \
python3-jupyterlab-server \
python3-linecache2 \
python3-loguru \
python3-lxml \
python3-mistune \
python3-mpi4py \
python3-nbclient \
python3-nbconvert \
python3-nbformat \
python3-nest-asyncio \
python3-netifaces \
python3-networkx \
python3-notebook \
python3-numpy \
python3-orderedmultidict \
python3-pandas \
python3-pandocfilters \
python3-parso \
python3-pexpect \
python3-pickleshare \
python3-pip \
python3-plotly \
python3-prettytable \
python3-prometheus-client \
python3-prompt-toolkit \
python3-protobuf \
Expand All @@ -229,7 +210,6 @@ apt -y install \
python3-requests \
python3-rich \
python3-rtree \
python3-scipy \
python3-send2trash \
python3-setuptools \
python3-setuptools-rust \
Expand Down Expand Up @@ -264,7 +244,6 @@ apt -y install \
python3-wcwidth \
python3-webcolors \
python3-wheel \
python3-widgetsnbextension \
python3-wrapt \
python3-xlsxwriter \
python3-xmltodict \
Expand Down
6 changes: 6 additions & 0 deletions _build/images/base/scripts/70_install_from_pip.sh
Original file line number Diff line number Diff line change
Expand Up @@ -8,23 +8,29 @@ set -e

echo "[INFO] Install support packages via PIP"
pip3 install --upgrade --no-cache-dir \
bottleneck \
control \
gobject \
ipympl \
jupyterlab \
libparse \
matplotlib \
matplotlib-inline \
maturin \
meson \
ninja \
numexpr \
numpy \
panda \
pandas \
pathspec \
pipdeptree \
prettyprinttree \
prettytable \
pyyaml \
scikit-build \
scikit-image \
scipy \
simanneal \
svgutils \
torch_geometric
Expand Down
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