Update to TB

.gitignore

@@ -11,3 +11,4 @@ src/user_config.tcl
 *.cvcrc
 *.out
 *.bkp
+.pycache

sim/tb_tempsens.sch

@@ -168,13 +168,22 @@ value="
 * Misc
 ****************
 .param fclk=10k
-.options method=gear maxord=2 klu
+.options method=gear maxord=2
 .temp 30
 
 .control
 tran 10u 30m
+<<<<<<< Updated upstream
 *tran 10u 20u
 write tb_tempsens.raw
+=======
+*tran 10u 1u
+
+let k=length(time)-1
+print st0[k] st1[k] st2[k] st3[k] st4[k] st5[k] st6[k] st7[k] > res.txt
+
+exit
+>>>>>>> Stashed changes
 .endc
 "}
 C {devices/gnd.sym} 220 -210 0 0 {name=l21 lab=GND}
@@ -193,7 +202,7 @@ C {devices/vsource.sym} 460 -260 0 0 {name=V23 value=0}
 C {devices/vsource.sym} 520 -260 0 0 {name=V24 value=0}
 C {devices/vsource.sym} 660 -250 0 0 {name=VCM value="0 pulse(0 1.8 1u 1n 1n \{0.5/fclk\} \{1/fclk\})"}
 C {devices/gnd.sym} 660 -210 0 0 {name=l4 lab=GND}
-C {devices/vsource.sym} 660 -400 0 0 {name=VRES value="0 pwl(0 1.8 \{0.5/fclk\} 1.8 \{0.5/fclk+1n\} 0)"}
+C {devices/vsource.sym} 660 -400 0 0 {name=VRES value="1.8 pwl(0 1.8 \{0.5/fclk\} 1.8 \{0.5/fclk+1n\} 0)"}
 C {devices/gnd.sym} 660 -360 0 0 {name=l5 lab=GND}
 C {devices/lab_wire.sym} 700 -440 0 1 {name=l6 sig_type=std_logic lab=rst}
 C {devices/lab_wire.sym} 700 -290 0 1 {name=l7 sig_type=std_logic lab=clk}
@@ -241,14 +250,12 @@ C {devices/lab_wire.sym} 1640 -460 0 1 {name=l30 sig_type=std_logic lab=st4}
 C {devices/lab_wire.sym} 1640 -440 0 1 {name=l31 sig_type=std_logic lab=st5}
 C {devices/lab_wire.sym} 1640 -420 0 1 {name=l32 sig_type=std_logic lab=st6}
 C {devices/lab_wire.sym} 1640 -400 0 1 {name=l33 sig_type=std_logic lab=st7}
-C {devices/spice_probe.sym} 1740 -540 0 0 {name=p1 attrs=""}
 C {devices/ammeter.sym} 60 -360 0 0 {name=Visupply}
-C {devices/spice_probe.sym} 1740 -520 0 0 {name=p2 attrs=""}
-C {devices/spice_probe.sym} 1740 -500 0 0 {name=p3 attrs=""}
-C {devices/spice_probe.sym} 1740 -480 0 0 {name=p4 attrs=""}
-C {devices/spice_probe.sym} 1740 -460 0 0 {name=p5 attrs=""}
-C {devices/spice_probe.sym} 1740 -440 0 0 {name=p6 attrs=""}
-C {devices/spice_probe.sym} 1740 -420 0 0 {name=p7 attrs=""}
-C {devices/spice_probe.sym} 1740 -400 0 0 {name=p8 attrs=""}
-C {devices/spice_probe.sym} 660 -440 0 0 {name=p9 attrs=""}
-C {devices/spice_probe.sym} 660 -290 0 0 {name=p10 attrs=""}
+C {devices/spice_probe.sym} 1680 -540 0 0 {name=p1 attrs=""}
+C {devices/spice_probe.sym} 1680 -520 0 0 {name=p2 attrs=""}
+C {devices/spice_probe.sym} 1680 -500 0 0 {name=p3 attrs=""}
+C {devices/spice_probe.sym} 1680 -480 0 0 {name=p4 attrs=""}
+C {devices/spice_probe.sym} 1680 -460 0 0 {name=p5 attrs=""}
+C {devices/spice_probe.sym} 1680 -440 0 0 {name=p6 attrs=""}
+C {devices/spice_probe.sym} 1680 -420 0 0 {name=p7 attrs=""}
+C {devices/spice_probe.sym} 1680 -400 0 0 {name=p8 attrs=""}

src/tempsense_paper.v

@@ -0,0 +1,37 @@
+module tempsense #( parameter NDAC=6, parameter NCAP=4 )(
+  input wire [NDAC-1:0] i_dat, input wire i_en, input wire i_prchrg_n,
+  output wire o_tmpdel);
+  wire dac_vout;
+  vdac #(.NBIT(NDAC)) dac (.i_dat(i_dat), .i_en(i_en), .vout(dac_vout));
+  wire tie0 = 1'b0, capn, del_n;
+  wire [NCAP-1:0] dummy;
+  sky130_fd_sc_hd__einvp_1 dcdc (.A(i_prchrg_n), .TE(dac_vout), .Z(capn));
+  sky130_fd_sc_hd__inv_1 inv1 (.A(capn), .Y(del_n));
+  sky130_fd_sc_hd__inv_1 inv2 (.A(del_n), .Y(o_tmpdel));
+  genvar i; generate
+    for (i=0; i<NCAP; i=i+1) begin : capload
+      sky130_fd_sc_hd__nand2_1 cap (.B(capn), .A(tie0), .Y(dummy[i]));
+    end endgenerate
+endmodule // tempsense
+module vdac #(parameter NBIT=6 )(
+  input wire [NBIT-1:0] i_dat, input wire i_en, output wire vout);
+  genvar i; generate 
+    for (i = 0; i<NBIT-1; i=i+1) begin : NPAR
+      vdac_cell #(.NPAR(2**i)) vdac_batch (
+        .i_sgn(i_dat[NBIT-1]), .i_dat(i_dat[i]), .i_en(i_en), .vout(vout));
+  end endgenerate
+  vdac_cell #(.NPAR(1)) vdac_single (
+    .i_sgn(1'b0), .i_dat(1'b0), .i_en(i_en & (~i_dat[NBIT-1])), .vout(vout));
+endmodule // vdac
+module vdac_cell #(parameter NPAR=4 )(
+  input wire i_sgn, input wire i_dat, input wire	i_en, output wire vout);
+  wire en_vref, en_pupd, npu_pd;
+  assign npu_pd  = ~i_dat;
+  assign en_pupd = i_en & (~(i_sgn^i_dat));
+  assign en_vref = i_en & (i_sgn^i_dat);
+  genvar i; generate
+    for (i=0; i<NPAR; i=i+1) begin : einvp_batch
+      sky130_fd_sc_hd__einvp_1 pupd (.A(npu_pd), .TE(en_pupd), .Z(vout));
+      sky130_fd_sc_hd__einvp_1 vref (.A(vout), .TE(en_vref), .Z(vout));
+  end endgenerate
+endmodule // vdac_cell