First draft of implementation

README.md

@@ -1,41 +1,7 @@
 ![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/test/badge.svg) ![](../../workflows/fpga/badge.svg)
 
-# Tiny Tapeout Verilog Project Template
+# Simple SPI Test
 
-- [Read the documentation for project](docs/info.md)
+(c) 2024 Harald Pretl, Institute for Integrated Circuits, Johannes Kepler University, Linz, Austria
 
-## What is Tiny Tapeout?
-
-Tiny Tapeout is an educational project that aims to make it easier and cheaper than ever to get your digital and analog designs manufactured on a real chip.
-
-To learn more and get started, visit https://tinytapeout.com.
-
-## Set up your Verilog project
-
-1. Add your Verilog files to the `src` folder.
-2. Edit the [info.yaml](info.yaml) and update information about your project, paying special attention to the `source_files` and `top_module` properties. If you are upgrading an existing Tiny Tapeout project, check out our [online info.yaml migration tool](https://tinytapeout.github.io/tt-yaml-upgrade-tool/).
-3. Edit [docs/info.md](docs/info.md) and add a description of your project.
-4. Adapt the testbench to your design. See [test/README.md](test/README.md) for more information.
-
-The GitHub action will automatically build the ASIC files using [OpenLane](https://www.zerotoasiccourse.com/terminology/openlane/).
-
-## Enable GitHub actions to build the results page
-
-- [Enabling GitHub Pages](https://tinytapeout.com/faq/#my-github-action-is-failing-on-the-pages-part)
-
-## Resources
-
-- [FAQ](https://tinytapeout.com/faq/)
-- [Digital design lessons](https://tinytapeout.com/digital_design/)
-- [Learn how semiconductors work](https://tinytapeout.com/siliwiz/)
-- [Join the community](https://tinytapeout.com/discord)
-- [Build your design locally](https://www.tinytapeout.com/guides/local-hardening/)
-
-## What next?
-
-- [Submit your design to the next shuttle](https://app.tinytapeout.com/).
-- Edit [this README](README.md) and explain your design, how it works, and how to test it.
-- Share your project on your social network of choice:
-  - LinkedIn [#tinytapeout](https://www.linkedin.com/search/results/content/?keywords=%23tinytapeout) [@TinyTapeout](https://www.linkedin.com/company/100708654/)
-  - Mastodon [#tinytapeout](https://chaos.social/tags/tinytapeout) [@matthewvenn](https://chaos.social/@matthewvenn)
-  - X (formerly Twitter) [#tinytapeout](https://twitter.com/hashtag/tinytapeout) [@tinytapeout](https://twitter.com/tinytapeout)
+This design implements a simple 8b input, 8b output freely programmable logic block with optional selectable feedback.

docs/info.md

@@ -9,12 +9,13 @@ You can also include images in this folder and reference them in the markdown. E
 
 ## How it works
 
-Explain how your project works
+A programmable 8b input, 8b output freely programmable logic block with optional internal feedback. This can serve many purposes, once an FPGA-style configuration SW is available.
 
 ## How to test
 
-Explain how to use your project
+- Load the logic block in serial mode.
+- Test the logic functionality by applying different digital inputs.
 
 ## External hardware
 
-List external hardware used in your project (e.g. PMOD, LED display, etc), if any
+Just a way to set digital inputs is needed, plus a way to check the digital outputs.

info.yaml

@@ -1,55 +1,56 @@
 # Tiny Tapeout project information
 project:
-  title:        ""      # Project title
-  author:       ""      # Your name
-  discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  ""      # One line description of what your project does
-  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
-  clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
+  title:        "Minilogix"
+  author:       "Harald Pretl"
+  discord:      "hpretl"
+  description:  "A configurable 8b in, 8b out logic block with optional feedback"
+  language:     "Verilog"
+  clock_hz:     20000000
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
-  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2 or 6x2
+  tiles: "2x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2 or 6x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
-  top_module:  "tt_um_example"
+  top_module:  "tt_um_hpretl_minilogix"
 
   # List your project's source files here.
   # Source files must be in ./src and you must list each source file separately, one per line.
   # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
   source_files:
-    - "project.v"
+    - "tt_um_hpretl_minilogix.v"
+    - "minilogix1.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
   # Inputs
-  ui[0]: ""
-  ui[1]: ""
-  ui[2]: ""
-  ui[3]: ""
-  ui[4]: ""
-  ui[5]: ""
-  ui[6]: ""
-  ui[7]: ""
+  ui[0]: "SPI clk (SCLK)"
+  ui[1]: "SPI data in (MOSI)"
+  ui[2]: "SPI load (CS)"
+  ui[3]: "select output byte (0 = low, 1 = high)"
+  ui[4]: "sinegen scale factor (LSB)"
+  ui[5]: "sinegen scale factor (MSB)"
+  ui[6]: "select ds-modulator input (0 = SPI register, 1 = sine generator)"
+  ui[7]: "order of delta-sigma modulator (0 = 1st, 1 = 2nd)"
 
   # Outputs
-  uo[0]: ""
-  uo[1]: ""
-  uo[2]: ""
+  uo[0]: "SPI data out (MISO)"
+  uo[1]: "cookie detected (loaded 0xCAFE)"
+  uo[2]: "XOR of SPI clk and SPI data in"
   uo[3]: ""
   uo[4]: ""
   uo[5]: ""
-  uo[6]: ""
-  uo[7]: ""
+  uo[6]: "inverted output of delta-sigma modulator"
+  uo[7]: "output of delta-sigma modulator"
 
   # Bidirectional pins
-  uio[0]: ""
-  uio[1]: ""
-  uio[2]: ""
-  uio[3]: ""
-  uio[4]: ""
-  uio[5]: ""
-  uio[6]: ""
-  uio[7]: ""
+  uio[0]: "register b0|8"
+  uio[1]: "register b1|9"
+  uio[2]: "register b2|10"
+  uio[3]: "register b3|11"
+  uio[4]: "register b4|12"
+  uio[5]: "register b5|13"
+  uio[6]: "register b6|14"
+  uio[7]: "register b7|15"
 
 # Do not change!
 yaml_version: 6

src/config.json

@@ -20,9 +20,6 @@
   "//": "Increase this if you are getting 'Synthesized memory size exceeds maximum allowed bits' error:",
   "SYNTH_MEMORY_MAX_BITS": 4096,
 
-  "//": "Setting to 1 may help decrease design area utilization / speed up routing:",
-  "ABC_AREA": 0,
-
   "//": "Configuration docs: https://openroad-flow-scripts.readthedocs.io/en/latest/user/FlowVariables.html",
 
   "//": "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!",

src/minilogix1.v

@@ -0,0 +1,71 @@
+/*
+* SPDX-FileCopyrightText: 2024 Harald Pretl
+* Johannes Kepler University, Institute for Integrated Circuits
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*      http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Freely programmable logic block with optional feedback
+*/
+
+`default_nettype none
+`ifndef __MINILOGIX1__
+`define __MINILOGIX1__
+
+module minilogix1 #(parameter NIN=8, NOUT=8) (
+	input wire						clk,
+	input wire [NIN-1:0]			i_input,
+	output reg [NOUT-1:0]			o_output,
+	input wire						i_load_en,
+	input wire						i_load_clk,
+	input wire						i_load_dat
+);
+
+	localparam NCFG = (NIN<NOUT) ? NIN : NOUT;
+
+	reg [NOUT*(2**NIN)+NCFG-1:0]	ram;
+	wire [NCFG-1:0]					input_sel_cfg;
+	wire [NIN-1:0]					ram_sel;
+
+	// last word in RAM is the input configuration for controlling the input mux
+	assign input_sel_cfg = ram[NOUT*(2**NIN)+NCFG-1 -: NCFG];
+
+	// if the input selection bit is 0, then the input is taken; otherwise the
+	// respective output is feed back
+	genvar j;
+	generate for(j=0; j<NCFG; j=j+1)
+		begin: input_selection
+			assign ram_sel[j] = input_sel_cfg[j] ? o_output[j] : i_input[j];
+		end
+	endgenerate
+
+	always @(posedge clk) begin
+		o_output <= ram[ram_sel*NOUT +: NOUT];
+	end
+
+	genvar k;
+	generate for(k=0; k<NOUT*(2**NIN)+NCFG-1; k=k+1)
+	begin: load_ram
+		always @(posedge i_load_clk) begin
+			if (i_load_en) begin
+				ram[0] <= i_load_dat;
+				ram[k+1] <= ram[k];
+			end
+		end
+	end
+	endgenerate
+
+endmodule // minilogix1
+
+`endif
+`default_nettype wire

src/project.v → src/tt_um_hpretl_minilogix.v

@@ -1,11 +1,12 @@
 /*
- * Copyright (c) 2024 Your Name
+ * Copyright (c) 2024 Harald Pretl, IIC@JKU
  * SPDX-License-Identifier: Apache-2.0
  */
 
 `default_nettype none
+`include "minilogix1.v"
 
-module tt_um_example (
+module tt_um_hpretl_minilogix (
     input  wire [7:0] ui_in,    // Dedicated inputs
     output wire [7:0] uo_out,   // Dedicated outputs
     input  wire [7:0] uio_in,   // IOs: Input path
@@ -16,12 +17,21 @@ module tt_um_example (
     input  wire       rst_n     // reset_n - low to reset
 );
 
+  assign uio_oe = 8'b0000000;  // using IO for input
+
+  minilogix1 #(.NIN(8), .NOUT(8)) logix (
+    .clk(clk),
+    .i_input(ui_in),
+    .o_output(uo_out),
+    .i_load_en(uio_in[0]),
+    .i_load_clk(uio_in[1]),
+    .i_load_dat(uio_in[2])
+  );
+
   // All output pins must be assigned. If not used, assign to 0.
-  assign uo_out  = ui_in + uio_in;  // Example: ou_out is the sum of ui_in and uio_in
-  assign uio_out = 0;
-  assign uio_oe  = 0;
+  assign uio_out[7:0] = 8'b000;
 
   // List all unused inputs to prevent warnings
-  wire _unused = &{ena, clk, rst_n, 1'b0};
+  wire _unused = &{ena, rst_n, uio_in[7:3], 1'b0};
 
-endmodule
+endmodule // tt_um_hpretl_minilogix

test/Makefile

@@ -5,7 +5,7 @@
 SIM ?= icarus
 TOPLEVEL_LANG ?= verilog
 SRC_DIR = $(PWD)/../src
-PROJECT_SOURCES = project.v
+PROJECT_SOURCES = tt_um_hpretl_minilogix.v
 
 ifneq ($(GATES),yes)
 

test/tb.v

@@ -24,7 +24,7 @@ module tb ();
   wire [7:0] uio_oe;
 
   // Replace tt_um_example with your module name:
-  tt_um_example user_project (
+  tt_um_hpretl_minilogix user_project (
       .ui_in  (ui_in),    // Dedicated inputs
       .uo_out (uo_out),   // Dedicated outputs
       .uio_in (uio_in),   // IOs: Input path