First implementation incl. docs

docs/info.md

@@ -9,12 +9,12 @@ You can also include images in this folder and reference them in the markdown. E
 
 ## How it works
 
-Explain how your project works
+A simple serial 16b register (mini SPI) with magic cookie detection is implemented.
 
 ## How to test
 
-Explain how to use your project
+Load the shift register in a serial way.
 
 ## External hardware
 
-List external hardware used in your project (e.g. PMOD, LED display, etc), if any
+Just a way to set digital inputs is needed. A scope for monitoring output signals would be good.

info.yaml

@@ -1,55 +1,56 @@
 # Tiny Tapeout project information
 project:
-  title:        ""      # Project title
-  author:       ""      # Your name
-  discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  ""      # One line description of what your project does
-  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
-  clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
+  title:        "SPI Test"
+  author:       "Harald Pretl"
+  discord:      "hpretl"
+  description:  "Simple SPI-based register file (for the testing the flow)"
+  language:     "Verilog"
+  clock_hz:     20000000
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2 or 6x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
-  top_module:  "tt_um_example"
+  top_module:  "tt_um_hpretl_spi"
 
   # List your project's source files here.
   # Source files must be in ./src and you must list each source file separately, one per line.
   # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
   source_files:
-    - "project.v"
+    - "tt_um_hpretl_spi.v"
+    - "chain1.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
   # Inputs
-  ui[0]: ""
-  ui[1]: ""
-  ui[2]: ""
+  ui[0]: "clk (SCLK"
+  ui[1]: "data_in (MOSI)"
+  ui[2]: "select output byte (0 = low, 1 = high)"
   ui[3]: ""
   ui[4]: ""
   ui[5]: ""
   ui[6]: ""
   ui[7]: ""
 
   # Outputs
-  uo[0]: ""
-  uo[1]: ""
-  uo[2]: ""
+  uo[0]: "data_out (MISO)"
+  uo[1]: "cookie detected (loaded 0xCAFE)"
+  uo[2]: "XOR of clk and data_in"
   uo[3]: ""
   uo[4]: ""
   uo[5]: ""
   uo[6]: ""
   uo[7]: ""
 
   # Bidirectional pins
-  uio[0]: ""
-  uio[1]: ""
-  uio[2]: ""
-  uio[3]: ""
-  uio[4]: ""
-  uio[5]: ""
-  uio[6]: ""
-  uio[7]: ""
+  uio[0]: "register b0|8"
+  uio[1]: "register b1|9"
+  uio[2]: "register b2|10"
+  uio[3]: "register b3|11"
+  uio[4]: "register b4|12"
+  uio[5]: "register b5|13"
+  uio[6]: "register b6|14"
+  uio[7]: "register b7|15"
 
 # Do not change!
 yaml_version: 6

src/chain1.v

@@ -4,21 +4,19 @@
     SPDX-License-Identifier: Apache-2.0
 
    Very simple scan chain with load register and magic cookie detection for
-   SG13G2 May'2024 run. Target is to test RTL2GDS flow for functionality. 
+   SG13G2 TinyTapeout Nov'2024 run. Target is to test RTL2GDS flow for functionality. 
 
    The output o_check is XOR of i_dat and i_load (pure logic in case all else
    fails).
 
-   8 pins available on testchiplet:
+   IO description:
 
-    1 = VDD
-    2 = VSS
-    3 = i_clk (like SPI SCLK)
-    4 = i_dat (like SPI MOSI)
-    5 = i_load (like SPI nCS)
-    6 = o_dat (like SPI MISO)
-    7 = o_det (magic cookie detected)
-    8 = o_check (XOR of i_dat and i_load)
+    i_clk (like SPI SCLK)
+    i_dat (like SPI MOSI)
+    i_load (like SPI nCS)
+    o_dat (like SPI MISO)
+    o_det (magic cookie detected)
+    o_check (XOR of i_dat and i_load)
 */
 
 `ifndef __CHAIN1__
@@ -60,4 +58,3 @@ module chain1 (
 
 endmodule // chain1
 `endif 
-

src/project.v → src/tt_um_hpretl_spi.v

@@ -1,11 +1,12 @@
 /*
- * Copyright (c) 2024 Your Name
+ * Copyright (c) 2024 Harald Pretl, IIC@JKU
  * SPDX-License-Identifier: Apache-2.0
  */
 
 `default_nettype none
+`include "chain1.v"
 
-module tt_um_example (
+module tt_um_hpretl_spi (
     input  wire [7:0] ui_in,    // Dedicated inputs
     output wire [7:0] uo_out,   // Dedicated outputs
     input  wire [7:0] uio_in,   // IOs: Input path
@@ -16,12 +17,25 @@ module tt_um_example (
     input  wire       rst_n     // reset_n - low to reset
 );
 
+  wire [15:0] out_w;
+
+  assign uio_oe = 8'b11111111;  // using IO for output
+  assign uio_out = ui_in[2] ? out_w[15:8] : out_w[7:0]; 
+
+  chain1 dut(
+    .i_clk(clk),
+    .i_dat(ui_in[0]),
+    .i_load(ui_in[1]),
+    .o_dat(uo_out[0]),
+    .o_det(uo_out[1]),
+    .o_check(uo_out[2]),
+    .o_data(out_w)
+  );
+
   // All output pins must be assigned. If not used, assign to 0.
-  assign uo_out  = ui_in + uio_in;  // Example: ou_out is the sum of ui_in and uio_in
-  assign uio_out = 0;
-  assign uio_oe  = 0;
+  assign uo_out[7:3] = 5'b10000;
 
   // List all unused inputs to prevent warnings
-  wire _unused = &{ena, clk, rst_n, 1'b0};
+  wire _unused = &{ena, rst_n, uio_in[7:0], ui_in[7:3], 1'b0};
 
-endmodule
+endmodule // tt_um_hpretl_spi