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brabo committed Jul 4, 2016
1 parent af88343 commit ab8c4a7
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Showing 32 changed files with 402 additions and 390 deletions.
24 changes: 12 additions & 12 deletions include/unicore-mx/lm3s/usart.h
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Expand Up @@ -80,27 +80,27 @@
/* Bits [3:0] - Reserved */

enum usart_stopbits {
USART_STOPBITS_1,
USART_STOPBITS_1_5,
USART_STOPBITS_2,
USART_STOPBITS_1,
USART_STOPBITS_1_5,
USART_STOPBITS_2,
};

enum usart_parity {
USART_PARITY_NONE,
USART_PARITY_ODD,
USART_PARITY_EVEN,
USART_PARITY_NONE,
USART_PARITY_ODD,
USART_PARITY_EVEN,
};

enum usart_mode {
USART_MODE_DISABLED,
USART_MODE_RX,
USART_MODE_TX,
USART_MODE_TX_RX,
USART_MODE_DISABLED,
USART_MODE_RX,
USART_MODE_TX,
USART_MODE_TX_RX,
};

enum usart_flowcontrol {
USART_FLOWCONTROL_NONE,
USART_FLOWCONTROL_RTS_CTS,
USART_FLOWCONTROL_NONE,
USART_FLOWCONTROL_RTS_CTS,
};

void usart_send(uint32_t usart, uint16_t data);
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17 changes: 8 additions & 9 deletions include/unicore-mx/lpc17xx/clock.h
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Expand Up @@ -90,7 +90,7 @@ LGPL License Terms @ref lgpl_license
#define CLK_PLL0STAT_PLOCK (1 << 26)
/* STAT Reserved: [31:27] */

#define PLL0_CFG_VAL(M,N) (((N-1) << 16) |(M-1))
#define PLL0_CFG_VAL(M, N) (((N-1) << 16) | (M-1))

/* PLL0 Feed sequence */
#define PLL_KICK0 0xAAUL
Expand Down Expand Up @@ -161,16 +161,15 @@ LGPL License Terms @ref lgpl_license
#define CLK_CLKOUTCFG_ACTIVITY (1 << 9)
/* Reserved: [31:10]*/

typedef struct
{
uint32_t m;
uint32_t n;
uint32_t cclkdiv;
}clock_scale_t;
typedef struct {
uint32_t m;
uint32_t n;
uint32_t cclkdiv;
} clock_scale_t;

typedef enum {
CLOCK_96MHZ,
CLOCK_120MHZ,
CLOCK_96MHZ,
CLOCK_120MHZ,
} clock_speed_t;

extern const clock_scale_t clock_scale[];
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16 changes: 8 additions & 8 deletions include/unicore-mx/lpc17xx/exti.h
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Expand Up @@ -21,21 +21,21 @@
#include <unicore-mx/cm3/common.h>
#include <unicore-mx/lpc17xx/memorymap.h>

#define EXTINT MMIO32(SYSCON_BASE + 0x140)
#define EXTMODE MMIO32(SYSCON_BASE + 0x148)
#define EXTPOLAR MMIO32(SYSCON_BASE + 0x14C)
#define EXTINT MMIO32(SYSCON_BASE + 0x140)
#define EXTMODE MMIO32(SYSCON_BASE + 0x148)
#define EXTPOLAR MMIO32(SYSCON_BASE + 0x14C)

#define EXTI0 0
#define EXTI1 1
#define EXTI2 2
#define EXTI3 3
#define EXTI0 0
#define EXTI1 1
#define EXTI2 2
#define EXTI3 3


enum exti_trigger_type {
EXTI_TRIGGER_RISING,
EXTI_TRIGGER_FALLING,
EXTI_TRIGGER_HIGH,
EXTI_TRIGGER_LOW
EXTI_TRIGGER_LOW
};

void exti_set_trigger(uint32_t extis, enum exti_trigger_type trig);
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44 changes: 22 additions & 22 deletions include/unicore-mx/lpc17xx/gpio.h
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Expand Up @@ -124,50 +124,50 @@ LGPL License Terms @ref lgpl_license

/* GPIO interrupt register map */
/* Interrupt enable rising edge */
#define GPIO0_IER MMIO32(GPIOINTERRUPT_BASE + 0x90)
#define GPIO2_IER MMIO32(GPIOINTERRUPT_BASE + 0xB0)
#define GPIO0_IER MMIO32(GPIOINTERRUPT_BASE + 0x90)
#define GPIO2_IER MMIO32(GPIOINTERRUPT_BASE + 0xB0)

/* Interrupt enable falling edge */
#define GPIO0_IEF MMIO32(GPIOINTERRUPT_BASE + 0x94)
#define GPIO2_IEF MMIO32(GPIOINTERRUPT_BASE + 0xB4)
#define GPIO0_IEF MMIO32(GPIOINTERRUPT_BASE + 0x94)
#define GPIO2_IEF MMIO32(GPIOINTERRUPT_BASE + 0xB4)

/* Interrupt status rising edge */
#define GPIO0_ISR MMIO32(GPIOINTERRUPT_BASE + 0x84)
#define GPIO2_ISR MMIO32(GPIOINTERRUPT_BASE + 0xA4)
#define GPIO0_ISR MMIO32(GPIOINTERRUPT_BASE + 0x84)
#define GPIO2_ISR MMIO32(GPIOINTERRUPT_BASE + 0xA4)

/* Interrupt status falling edge */
#define GPIO0_ISF MMIO32(GPIOINTERRUPT_BASE + 0x88)
#define GPIO2_ISF MMIO32(GPIOINTERRUPT_BASE + 0xA8)
#define GPIO0_ISF MMIO32(GPIOINTERRUPT_BASE + 0x88)
#define GPIO2_ISF MMIO32(GPIOINTERRUPT_BASE + 0xA8)

/* Interrupt clear */
#define GPIO0_IC MMIO32(GPIOINTERRUPT_BASE + 0x8C)
#define GPIO1_IC MMIO32(GPIOINTERRUPT_BASE + 0xAC)
#define GPIO0_IC MMIO32(GPIOINTERRUPT_BASE + 0x8C)
#define GPIO1_IC MMIO32(GPIOINTERRUPT_BASE + 0xAC)

/* Overall interrupt status */
#define GPIO_IS MMIO32(GPIOINTERRUPT_BASE + 0x80)
#define GPIO_IS MMIO32(GPIOINTERRUPT_BASE + 0x80)


#define GPIO_AF0 0x00
#define GPIO_AF1 0x01
#define GPIO_AF2 0x02
#define GPIO_AF3 0x03
#define GPIO_AF0 0x00
#define GPIO_AF1 0x01
#define GPIO_AF2 0x02
#define GPIO_AF3 0x03

#define GPIO_PUPD_PULLUP 0x00
#define GPIO_PUPD_REPEATER 0x01
#define GPIO_PUPD_NONE 0x02
#define GPIO_PUPD_PULLDOWN 0x03
#define GPIO_PUPD_PULLUP 0x00
#define GPIO_PUPD_REPEATER 0x01
#define GPIO_PUPD_NONE 0x02
#define GPIO_PUPD_PULLDOWN 0x03

#define GPIO_MODE_INPUT 0x00
#define GPIO_MODE_OUTPUT 0x01
#define GPIO_MODE_AF 0x02
#define GPIO_MODE_ANALOG 0x03
#define GPIO_MODE_AF 0x02
#define GPIO_MODE_ANALOG 0x03

BEGIN_DECLS

void gpio_set(uint32_t gpioport, uint32_t gpios);
void gpio_clear(uint32_t gpioport, uint32_t gpios);
void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint32_t gpios);
void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down,uint32_t gpios);
void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint32_t gpios);
uint16_t gpio_get(uint32_t gpioport, uint32_t gpios);

END_DECLS
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44 changes: 22 additions & 22 deletions include/unicore-mx/lpc17xx/uart.h
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Expand Up @@ -21,9 +21,9 @@
#include <unicore-mx/cm3/common.h>

/* --- Universal Asynchronous Receiver Transmitter (UART) */
#define UART_RBR(x) MMIO32((x) + 0x0000)
#define UART_THR(x) MMIO32((x) + 0x0000)
#define UART_DLL(x) MMIO32((x) + 0x0000)
#define UART_RBR(x) MMIO32((x) + 0x0000)
#define UART_THR(x) MMIO32((x) + 0x0000)
#define UART_DLL(x) MMIO32((x) + 0x0000)
#define UART_DLM(x) MMIO32((x) + 0x0004)
#define UART_IER(x) MMIO32((x) + 0x0004)
#define UART_IIR(x) MMIO32((x) + 0x0008)
Expand All @@ -50,18 +50,18 @@
#define UART_ABT_II (0x01 << 9)
#define UART_ABE_II (0x01 << 8)
/* Bits 5:4 reserved */
#define UART_IIR_MASK (0x07 << 1)
#define UART_IIR_MASK (0x07 << 1)
/* Interrupt type: */
#define UART_IIR_RLS (0x03 << 1)
#define UART_IIR_RDA (0x02 << 1)
#define UART_IIR_CTI (0x06 << 1)
#define UART_IIR_THE (0x01 << 1)
#define UART_IIR_RLS (0x03 << 1)
#define UART_IIR_RDA (0x02 << 1)
#define UART_IIR_CTI (0x06 << 1)
#define UART_IIR_THE (0x01 << 1)
#define UART_IEN_II (0x01 << 0)


/* compatibility API for interrupt source detection */
#define USART_SR_TXE UART_IIR_THE
#define USART_SR_RXNE UART_IIR_RDA
#define USART_SR_TXE UART_IIR_THE
#define USART_SR_RXNE UART_IIR_RDA

/* UART Line Status Register (UART_LSR) */
/* Bits [31:8] - Reserved */
Expand All @@ -79,27 +79,27 @@
/* TODO: Other registries, according to datasheet */

enum usart_stopbits {
USART_STOPBITS_1,
USART_STOPBITS_1_5,
USART_STOPBITS_2,
USART_STOPBITS_1,
USART_STOPBITS_1_5,
USART_STOPBITS_2,
};

enum usart_parity {
USART_PARITY_NONE,
USART_PARITY_ODD,
USART_PARITY_EVEN,
USART_PARITY_NONE,
USART_PARITY_ODD,
USART_PARITY_EVEN,
};

enum usart_mode {
USART_MODE_DISABLED,
USART_MODE_RX,
USART_MODE_TX,
USART_MODE_TX_RX,
USART_MODE_DISABLED,
USART_MODE_RX,
USART_MODE_TX,
USART_MODE_TX_RX,
};

enum usart_flowcontrol {
USART_FLOWCONTROL_NONE,
USART_FLOWCONTROL_RTS_CTS,
USART_FLOWCONTROL_NONE,
USART_FLOWCONTROL_RTS_CTS,
};

void usart_send(uint32_t usart, uint16_t data);
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4 changes: 2 additions & 2 deletions include/unicore-mx/lpc43xx/gpdma.h
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Expand Up @@ -43,8 +43,8 @@ extern "C" {

typedef struct gpdma_lli_t gpdma_lli_t;
struct gpdma_lli_t {
void* csrcaddr;
void* cdestaddr;
void *csrcaddr;
void *cdestaddr;
uint32_t clli;
uint32_t ccontrol;
};
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2 changes: 1 addition & 1 deletion include/unicore-mx/sam/4l/gpio.h
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Expand Up @@ -177,7 +177,7 @@
#define GPIO_VERSION(X) MMIO32((X) + 0x1fc)

enum gpio_mode {
// Peripherals
/* Peripherals */
GPIO_MODE_A = 0,
GPIO_MODE_B,
GPIO_MODE_C,
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2 changes: 1 addition & 1 deletion include/unicore-mx/sam/4l/pm.h
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Expand Up @@ -107,7 +107,7 @@
#define PM_MCCTRL_MCSEL_SHIFT 0
#define PM_MCCTRL_MCSEL_MASK 3

// Values common for CPUSEL and PBxSEL
/* Values common for CPUSEL and PBxSEL */
#define PM_CKSEL_DIV (1 << 7)
#define PM_CKSEL_MASK (3)

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