Skip to content

v2025.06.08

Latest
Latest
Compare
Choose a tag to compare
@marjevan marjevan released this 11 Jun 17:39
v2025.06.08
dc6bdbe
This commit was created on GitHub.com and signed with GitHub’s verified signature.
GPG key ID: B5690EEEBB952194
Verified
Learn about vigilant mode.

This release aligns XED with Intel’s latest architecture specifications, including:

  • Intel® SDM Revision 087
  • Intel® ISE Revision 057
  • Intel® AVX10.2 Revision 5.0

Key ISA-related changes:

  • Dropped support for AVX10/256-specific architectural features, including YMM embedded rounding and AVX10 VL-specific CPUID enumerations
  • Updated CPUID sensitivity for various AVX10.2 instructions
  • Updated exception class handling for several AVX512 instructions

General

  • Modified arguments of the xed_operand_print() decoder API to correctly represent the destination EVEX operand (the old signature is deprecated and replaced)
  • Restructured XED examples for improved clarity, naming, and usability
  • Improved XedPy with more robust initialization and initial high-level Python encode APIs
  • Migrated internal types to use stdint.h exclusively
  • Added ENC2 support for REX2 prefix encoding with EGPR operands

Fixes

  • Fixed many build exclusion options; deprecated several build flavors in favor of --no-avx512 as the minimal build kit (Fixes #336)
  • Encoder: fixed AMX encoding for non-index SIBMEM operands
  • Added missing and removed incorrect non-temporal memory hints
  • Resolved Python 3.12 compatibility warnings (Closes #346)
  • Fixed AMD INVLPGB operand specification (Closes #345)
  • Corrected AMD PREFETCH_EXCLUSIVE mnemonic name (Fixes #215)
  • Updated instruction definitions for various AVX512 instructions
  • Applied various documentation improvements (Fixes #347)

Full Changelog: v2025.03.02...v2025.06.08

Assets 2
Loading