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Update Pixel 8 Pro CPU feature flags
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mariecwhite committed Jan 4, 2024
1 parent ca9244f commit 100f746
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Showing 5 changed files with 9 additions and 5 deletions.
1 change: 1 addition & 0 deletions .github/workflows/run_mobile_comparative_benchmark.yml
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schedule:
# Scheduled to run at 09:00 UTC and 21:00 UTC.
- cron: '0 09,21 * * *'
pull_request:

concurrency:
# A PR number if a pull request and otherwise the commit hash. This cancels
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from openxla.benchmark import def_types
from openxla.benchmark.comparative_suite import utils

PARENT_GCS_DIR = "https://storage.googleapis.com/iree-model-artifacts/jax/jax_models_0.4.20_1699872537"
PARENT_GCS_DIR = "https://storage.googleapis.com/iree-model-artifacts/jax/jax_models_0.4.23_1702848353"
ARTIFACTS_DIR_URL_TEMPLATE = string.Template(PARENT_GCS_DIR + "/${name}")

T5_JAX_IMPL = def_types.ModelImplementation(
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)) + [
GPT2LMHEAD_PIPELINE_JAX_1X4XI32,
T5_SMALL_FP32_JAX_1X128XI32,
VIT_CLASSIFICATION_JAX_3X224X224XF32,
]
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from openxla.benchmark import def_types
from openxla.benchmark.comparative_suite import utils

PARENT_GCS_DIR = "https://storage.googleapis.com/iree-model-artifacts/tflite/tflite_models_1701944859"
PARENT_GCS_DIR = "https://storage.googleapis.com/iree-model-artifacts/tflite/tflite_models_1703027804"

ARTIFACTS_DIR_URL_TEMPLATE = string.Template(PARENT_GCS_DIR + "/${name}")

TFLITE_MODEL_IMPL = def_types.ModelImplementation(
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module_path=f"{utils.MODELS_MODULE_PATH}.tflite.tflite_model",
)

JAX_MODELS_GCS_DIR = "https://storage.googleapis.com/iree-model-artifacts/jax/jax_models_0.4.21_1701943542"
JAX_MODELS_GCS_DIR = "https://storage.googleapis.com/iree-model-artifacts/jax/jax_models_0.4.23_1702848353"

BERT_BASE_FP32_TFLITE_I32_INPUT_SEQUENCE_TEMPLATE = utils.ModelTemplate(
name=utils.SEQ_LEN_NAME("BERT_BASE_FP32_TFLITE_I32"),
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2 changes: 1 addition & 1 deletion experimental/iree/compile_workloads.py
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],
"pixel-8-pro": [
"--iree-llvmcpu-target-triple=aarch64-none-linux-android34",
"--iree-llvmcpu-target-cpu-features=+fp-armv8,+neon,+crc,+lse,+rdm,+ras,+rcpc,+dotprod,+v9a,+sb,+ssbs,+fullfp16,+fp16fml,+i8mm,+bf16,+flagm"
"--iree-llvmcpu-target-cpu-features=+v9a,+fullfp16,fp-armv8,+neon,+aes,+sha2,+crc,+lse,+rdm,+complxnum,+rcpc,+sha3,+sm4,+dotprod,+fp16fml,+dit,+flagm,+ssbs,+sb,+sve2-aes,+sve2-bitperm,+sve2-sha3,+sve2-sm4,+altnzcv,+fptoint,+bf16,+i8mm,+bti,+mte,+pauth,+perfmon,+predres,+spe,+ras"
],
}

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3 changes: 2 additions & 1 deletion experimental/iree/compile_workloads.sh
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Expand Up @@ -55,7 +55,8 @@ declare -a ANDROID_BENCHMARKS=(
"models/VIT_CLASSIFICATION_DYN_QUANT_TFLITE_3X224X224XF32/.+"
"models/VIT_CLASSIFICATION_INT8_TFLITE_3X224X224XINT8/.+"
"models/BERT_BASE_FP32_JAX_I32_SEQLEN.+/.+"
"models/BERT_BASE_FP16_JAX_I32_SEQLEN.+/.+"
# Disable sequence lengths >8 due to https://github.com/openxla/iree/issues/16042.
"models/BERT_BASE_FP16_JAX_I32_SEQLEN8/.+"
"models/T5_4CG_SMALL_FP32_JAX_1X128XI32_GEN.+/.+"
"models/SD_PIPELINE_FP32_JAX_64XI32_BATCH1/.+"
"models/SD_PIPELINE_FP16_JAX_64XI32_BATCH1/.+"
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