Disable failing tests on ARM64 and RISCV64

iree-org · Aug 26, 2024 · dcc5e11 · dcc5e11
1 parent 3818827
commit dcc5e11
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Showing 2 changed files with 50 additions and 4 deletions.
diff --git a/tests/e2e/regression/BUILD.bazel b/tests/e2e/regression/BUILD.bazel
@@ -8,6 +8,7 @@
 # These should focus on support by IREE itself, not for issues with specific runner tools.
 # Place those tests in tools/test/
 
+load("//build_tools/bazel:build_defs.oss.bzl", "iree_cmake_extra_content")
 load("//build_tools/bazel:iree_check_test.bzl", "iree_check_single_backend_test_suite")
 load("//build_tools/bazel:iree_lit_test.bzl", "iree_lit_test_suite")
 
@@ -72,9 +73,8 @@ iree_check_single_backend_test_suite(
 )
 
 iree_check_single_backend_test_suite(
-    name = "check_regression_llvm-cpu",
+    name = "check_regression_llvm-cpu-1",
     srcs = [
-        "layernorm.mlir",
         "lowering_config.mlir",
         "pack_pad_transpose_1x9_into_2x4x8x4_issue_12546.mlir",
     ] + BACKEND_TESTS,
@@ -83,6 +83,33 @@ iree_check_single_backend_test_suite(
     target_backend = "llvm-cpu",
 )
 
+iree_cmake_extra_content(
+    content = """
+# This test has a numeric mismatch on these backends
+# https://github.com/llvm/llvm-project/issues/105869
+if(NOT IREE_ARCH STREQUAL "arm_64"
+  AND NOT IREE_ARCH STREQUAL "riscv_64" )
+""",
+    inline = True,
+)
+
+iree_check_single_backend_test_suite(
+    name = "check_regression_llvm-cpu-2",
+    srcs = [
+        "layernorm.mlir",
+    ],
+    driver = "local-task",
+    input_type = "stablehlo",
+    target_backend = "llvm-cpu",
+)
+
+iree_cmake_extra_content(
+    content = """
+endif()  # NOT IREE_ARCH STREQUAL "arm_64" AND NOT IREE_ARCH STREQUAL "riscv_64"
+""",
+    inline = True,
+)
+
 iree_check_single_backend_test_suite(
     name = "check_regression_tosa_llvm-cpu",
     srcs = [

diff --git a/tests/e2e/regression/CMakeLists.txt b/tests/e2e/regression/CMakeLists.txt
@@ -48,7 +48,7 @@ iree_check_single_backend_test_suite(
 
 iree_check_single_backend_test_suite(
   NAME
-    check_regression_llvm-cpu
+    check_regression_llvm-cpu-1
   SRCS
     "dynamic_abs.mlir"
     "dynamic_add.mlir"
@@ -59,7 +59,6 @@ iree_check_single_backend_test_suite(
     "dynamic_torch_index_select_scalar.mlir"
     "dynamic_torch_index_select_vector.mlir"
     "i1_inlined_constant.mlir"
-    "layernorm.mlir"
     "linalg_ops.mlir"
     "lowering_config.mlir"
     "pack_pad_transpose_1x9_into_2x4x8x4_issue_12546.mlir"
@@ -76,6 +75,26 @@ iree_check_single_backend_test_suite(
     "stablehlo"
 )
 
+# This test has a numeric mismatch on these backends
+# https://github.com/llvm/llvm-project/issues/105869
+if(NOT IREE_ARCH STREQUAL "arm_64"
+  AND NOT IREE_ARCH STREQUAL "riscv_64" )
+
+iree_check_single_backend_test_suite(
+  NAME
+    check_regression_llvm-cpu-2
+  SRCS
+    "layernorm.mlir"
+  TARGET_BACKEND
+    "llvm-cpu"
+  DRIVER
+    "local-task"
+  INPUT_TYPE
+    "stablehlo"
+)
+
+endif()  # NOT IREE_ARCH STREQUAL "arm_64" AND NOT IREE_ARCH STREQUAL "riscv_64"
+
 iree_check_single_backend_test_suite(
   NAME
     check_regression_tosa_llvm-cpu