tests + small logic fix

src/disassembler/parser.rs

@@ -579,69 +579,73 @@ pub fn parse_instruction(bytes: &[u8], ip: usize) -> Result<(Instruction, usize)
         0xCF => Ok((IR::Iret, 1)),
         // Logic instructions
         0xD0..=0xD3 => {
-            // TODO: v = 0 "count" = 1, v = 1 "count" = CL
-            let _v = (opcode & 0x1) != 0;
             let w = (opcode & 0x1) != 0;
             if bytes.len() < 2 {
                 return Err(ParseError::UnexpectedEOF);
             }
 
+            // v = 0 "count" = 1, v = 1 "count" = CL
+            let src = match (opcode & 0x2) != 0 {
+                true => Operand::Register(Register::CL),
+                false => Operand::Immediate(1),
+            };
+
             let (_, rm, bytes_consumed) = parse_mod_reg_rm_bytes(&bytes[1..], w)?;
             let bits = (bytes[1] & 0x38) >> 3;
             match bits {
                 // SHL/SAL
                 0b100 => Ok((
                     IR::Shl {
                         dest: rm,
-                        src: Operand::Immediate(1),
+                        src,
                     },
                     bytes_consumed + 1,
                 )),
                 // SHR
                 0b101 => Ok((
                     IR::Shr {
                         dest: rm,
-                        src: Operand::Immediate(1),
+                        src,
                     },
                     bytes_consumed + 1,
                 )),
                 // SAR
                 0b111 => Ok((
                     IR::Sar {
                         dest: rm,
-                        src: Operand::Immediate(1),
+                        src,
                     },
                     bytes_consumed + 1,
                 )),
                 // ROL
                 0b000 => Ok((
                     IR::Rol {
                         dest: rm,
-                        src: Operand::Immediate(1),
+                        src,
                     },
                     bytes_consumed + 1,
                 )),
                 // ROR
                 0b001 => Ok((
                     IR::Ror {
                         dest: rm,
-                        src: Operand::Immediate(1),
+                        src,
                     },
                     bytes_consumed + 1,
                 )),
                 // RCL
                 0b010 => Ok((
                     IR::Rcl {
                         dest: rm,
-                        src: Operand::Immediate(1),
+                        src,
                     },
                     bytes_consumed + 1,
                 )),
                 // RCR
                 0b011 => Ok((
                     IR::Rcr {
                         dest: rm,
-                        src: Operand::Immediate(1),
+                        src,
                     },
                     bytes_consumed + 1,
                 )),

src/tests.rs

@@ -47,3 +47,23 @@ fn test_c_2() {
 fn test_c_3() {
     assert_disassemble("3.c");
 }
+
+#[test]
+fn test_c_4() {
+    assert_disassemble("4.c");
+}
+
+#[test]
+fn test_c_5() {
+    assert_disassemble("5.c");
+}
+
+#[test]
+fn test_c_6() {
+    assert_disassemble("6.c");
+}
+
+#[test]
+fn test_c_7() {
+    assert_disassemble("7.c");
+}