Note that this code has been released under the GNU GPLv3 License https://www.gnu.org/licenses/
I hope you find it useful.
Description: Implementation of scanning 8-digit 7-segment display with PWM dimming in Verilog for the Nexys A7-50T development board by Digilent
ToDo / Changes:
12.23.2020 This is my second working FPGA project in Verilog, no synchronization methods have been implemented yet, and naming conventions are all amuck. In addition, there's some code that is likely to synthesize strangely. This code is pending some major refactoring.